Lead Product Validation Engineer (SystemVerilog/UVM)

Location: Zhubei, Taiwan

Company

hirify.global develops computational software, hardware, and intellectual property for electronic design across chip, board, and system applications.

What you will do

• Validate system-level features across Palladium, Protium, and Solutions products and protocols.
• Develop and execute validation plans, test specifications, and regression strategies.
• Build, maintain, and support automated test harnesses and validation environments.
• Analyze regression failures and drive issue resolution with R&D, release, product engineering, and customer teams.
• Support release readiness, weekly releases, EHF releases, ISR validation, and customer issue reproduction.
• Track quality metrics, test coverage, and release risks, and present status to management.

Requirements

• Strong SystemVerilog and UVM verification knowledge.
• Experience with debugging, failure analysis, test automation, and regression infrastructure.
• Proficiency in Linux/Unix environments and scripting with Python, Tcl, or Shell.
• Knowledge of Jira/CCR workflows and emulation or prototyping platforms.
• Ability to independently own medium to large validation projects and create strategies with minimal supervision.
• BS/MS degree in electrical engineering, computer engineering, or computer science, with several years of verification or validation experience.

Nice to have

• Experience with protocol/IP validation, software validation, or system-level testing.
• Strong written and verbal communication skills.

Culture & Benefits

• Opportunities to work on cutting-edge technology and contribute to impactful electronic design solutions.
• Employee-friendly policies supporting physical and mental well-being.
• Career development and multiple learning opportunities.
• Collaborative One hirify.global – One Team culture.
• Diverse team environment focused on customer success.