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6 дней назад

IC PDK Development Engineer

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
UK
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
IC PDK Development Engineer (Semiconductor/Quantum Computing): Architecting, building, and maintaining custom process design kits and physical verification enablements for silicon quantum processors with an accent on Cadence Virtuoso, SKILL PCells, and Calibre DRC/LVS rule decks. Focus on integrating foundry PDKs, enabling cryogenic CMOS and silicon spin-qubit layouts, and debugging complex physical verification errors.

Location: London, UK; work is based around the Islington laboratory.

Company

hirify.global is a London-based quantum computing start-up developing silicon-chip quantum processors for applications including materials modelling, medicine, artificial intelligence, and cybersecurity.

What you will do

  • Architect, build, and maintain custom process design kits and physical verification enablements.
  • Develop PDK components including schematic symbols, SKILL PCells, and custom DRC and LVS decks.
  • Develop, qualify, and maintain Calibre SVRF rule decks for non-standard and cryogenic CMOS layout constraints.
  • Integrate foundry PDKs into Cadence Virtuoso, including library extensions, layer maps, and device callbacks.
  • Collaborate with IC designers and layout engineers on physical verification and layout automation practices.
  • Document work for peer review and evaluate layout and enablement work from other team members.

Requirements

  • Degree in Electronic Engineering, IC Layout, Computer Science, or a related physical science or engineering discipline.
  • 5+ years of hands-on industry experience in IC PDK development and PDK enablement flow management.
  • Proficiency in Cadence SKILL PCell coding and Virtuoso PDK customization.
  • Proficiency with Siemens Calibre physical verification tools and SVRF rule writing for DRC and LVS decks.
  • Experience debugging complex DRC and LVS errors in analog, mixed-signal, or custom digital layout environments.
  • Strong analytical, problem-solving, communication, self-management, and peer-review skills.

Nice to have

  • Experience with advanced deep-submicron CMOS nodes, including 40nm, 28nm, or below, and layout-dependent effects.
  • Expertise in Cadence Virtuoso, SKILL/SKILL++, and Siemens Calibre.
  • Familiarity with MOSFET device modelling integration such as BSIM or Verilog-A, or cryogenic device enablement.
  • Awareness of semiconductor quantum dots or silicon spin-qubit fundamentals.

Culture & Benefits

  • Interdisciplinary collaboration across quantum physics, IC design, quantum computing theory, and software engineering.
  • Research and development environment focused on scalable silicon-based quantum computers.
  • Competitive salary and share options scheme.
  • Contributory pension scheme, private medical insurance, and life assurance.
  • Cycle-to-work scheme and flexible working.

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