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6 дней назад

Digital IC Design Manager

Формат работы
onsite
Тип работы
fulltime
Грейд
lead
Английский
b2
Страна
Canada
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Текст:
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TL;DR
Digital IC Design Manager (ASIC/AR Displays): Managing a team of digital and physical design engineers building display ICs for Snap's Specs AR eyewear with an accent on RTL design, DFT, floorplanning, place-and-route, and timing closure. Focus on executing digital implementation flows, integrating internal and analog IP, and leading tool automation with Cadence and Siemens toolchains.

Location: Onsite in Vancouver, Canada — Snap's "Default Together" policy requires office work 4+ days per week.

Company

hirify.global develops Snapchat, Bitmoji, and Specs — advanced AR eyewear with a proprietary OS; the MicroDisplay Electronics and Software team builds state-of-the-art microdisplays for Specs.

What you will do

  • Manage a small team of digital designers and physical design engineers creating RTL code and its physical implementation for display ASICs
  • Work closely with chip architects, verification, analog design, and test functions on a Big-D, Big-A ASIC
  • Execute and improve RTL-to-GDS digital implementation flows for display ICs
  • Perform or manage logic design, DFT, chip floorplanning, place-and-route, timing closure, physical verification, synthesis, DFT insertion, and LEC
  • Specify and configure EDA tools and create automation
  • Hire and manage additional staff; may initially include individual contributor work

Requirements

  • BSEE or MSEE
  • 10+ years of directly applicable experience in physical design / digital implementation
  • Minimum 3 years of experience in a management role, including performance management, hiring, and promotion
  • Strong working knowledge of logic design, RTL coding, and associated functions (lint, CDC, LEC, DFT)
  • Strong working knowledge of digital implementation and integration of external/internal design IP, including analog blocks
  • Strong working knowledge of Cadence Innovus, Tempus, Genus, and PVS tools or equivalents, plus Mentor/Siemens Calibre tool suite

Nice to have

  • Knowledge of analog, mixed-signal circuit design, and custom layout
  • Experience with Siemens QuestaSim, Veloce emulation, Tessent DFT, Conformal LEC, or Virtuoso custom layout tools

Culture & Benefits

  • Equal opportunity employer committed to diverse teams
  • Paid parental leave and comprehensive medical coverage
  • Emotional and mental health support programs
  • Compensation packages including RSU equity

Salary: US pay zones range from $195,000–$343,000 annually depending on location (US zones; this role is based in Vancouver).

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