Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Зарплата и рынок
Очень мало
$128к-191к/год
$180к$200кмедиана$230к
По похожим ролям (50) ~ $200к/год
На СНГ рынке: $4.2к/мес ($3.5к - $5к)
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Роль дает возможность работать на стыке верификации ASIC и развивающихся AI-агентов в известной полупроводниковой компании, но зарплата ниже ориентира для похожих вакансий, а задачи требуют глубокой экспертизы сразу в двух областях.
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Ниже рыночного уровняШирокий набор задачСовременные технологииФокус на AIБонусы и акции
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Sr. Staff CAD-ASIC Design Verification Agentic Workflow (AI) (ASIC verification/Agentic AI): Developing and deploying agentic workflows for ASIC verification with an accent on regression analysis, failure triage, coverage closure, and integration with EDA tools. Focus on building LLM-based assistants, multi-agent orchestration, automated test and assertion generation, and scalable verification infrastructure.
Location: Santa Clara, California, United States
Expected base pay: $127,630–$191,200 per year, plus eligibility for bonus and equity plans.
Company
hirify.global develops semiconductor solutions that provide essential infrastructure for enterprise, cloud, AI, and carrier systems.
What you will do
Develop and deploy agentic AI workflows for ASIC design verification.
Automate regression analysis, failure triage, root-cause identification, and coverage closure.
Build AI agents that interact with EDA tools, simulation environments, and verification databases.
Integrate LLM-based assistants into verification flows and create workflows for test generation, assertion generation, UVM code creation, bug analysis, coverage improvement, and documentation.
Develop scalable infrastructure for agent orchestration and multi-agent collaboration.
Collaborate with design, DV, CAD, and methodology teams to improve verification productivity.
Requirements
BS or MS degree in Electrical Engineering, Computer Engineering, or a related field.
4+ years of ASIC design verification experience.
Strong knowledge of SystemVerilog, UVM, SVA, functional coverage, and constrained-random verification.
Experience with simulation-based verification, formal verification, emulation, or FPGA prototyping, with a strong understanding of SoC and IP verification methodologies.
Experience with LLMs, agent frameworks, prompt engineering, AI workflow orchestration, multi-agent systems, autonomous planning, tool calling, and function orchestration.
Experience with VCS/Verdi, Xcelium/Jasper, Siemens Questa, coverage and regression management tools, and scripting languages.
Culture & Benefits
Eligibility for bonus and equity plans, including new-hire equity grants and annual equity refreshers.
Employee stock purchase plan with a two-year lookback.
Family support programs and mental health resources.
Recognition and service awards.
Export-controlled technology access may require an export license review under U.S. regulations.
AI tools, recording tools, and automated assistants are not permitted during interviews.
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