Principal Application Engineer (ASIC Physical Design)

Location: Shanghai, China

Company

hirify.global develops technology solutions and supports advanced electronic design work.

What you will do

• Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, and timing closure.
• Execute power and signal integrity signoff, physical verification, DRC/LVS/Antenna checks, EM/IR signoff, and DFM closure.
• Work on low-power and high-speed designs using the latest technology nodes.
• Participate in or lead next-generation physical design methodology and flow development.
• Collaborate closely with RTL design teams to support successful tapeouts.

Requirements

• BS or MS degree in Electrical Engineering or Computer Science.
• 3+ years of hands-on experience in physical design and verification.
• Experience with ASIC design flows, hierarchical physical design strategies, methodologies, and deep sub-micron technology issues.
• Strong knowledge of low-power design, DFT, static timing analysis and closure, data skew balancing, duty-cycle adjustment, EM/IR drop, crosstalk analysis, formal verification, physical verification, DFM, and place and route.
• Ability to work independently, take responsibility for varied technical tasks, and verify, test, and characterize designs.
• Good English communication skills and the ability to work effectively as part of a team.

Culture & Benefits

• Opportunity to work on challenging designs across multiple technology nodes.
• Environment focused on leadership, innovation, and impactful technology work.