Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
Пожаловаться
Зарплата и рынок
Выше рынка
$210к-390к/год
$170к$200кмедиана$230к
По похожим ролям (50) ~ $200к/год
На СНГ рынке: $4.7к/мес ($3.2к - $5.9к)
85
Хорошая вакансия
развернуть
Роль четко определена с акцентом на технологии EDA и предлагает конкурентоспособную зарплату выше рыночной, что делает ее привлекательной для опытных инженеров.
Кликните для подробной информации
Сильный технический фокусСотрудничество в культуреГеографически распределенная команда
Оценка от Hirify AI
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Подключить Plus
Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Senior Software Architect (EDA): Architecting and enhancing Xcelium RTL/logic simulation and timing constraints verification technology for future AI and hyperscale chip designs with an accent on C/C++ performance optimization, SDC constraints, and multi-billion-node graph algorithms. Focus on designing scalable concurrent algorithms, reducing compilation time and memory footprint, and leading junior engineers in a distributed semiconductor software team.
Location: San Jose, California, United States
Annual salary: $210,000–$390,000, plus potential bonus, equity, and benefits.
Company
hirify.global develops electronic design automation technology, including the Xcelium logic simulator, for semiconductor design and verification.
What you will do
Enhance and support the Xcelium RTL/logic simulator engine and add new capabilities.
Develop and improve timing constraints verification technology used inside Xcelium.
Design, tune, and innovate graph algorithms for SDC constraints on multi-billion-node graphs.
Analyze bottlenecks and implement C/C++ performance optimizations to improve compilation speed and memory usage.
Lead junior engineers and collaborate with geographically distributed team members.
Contribute to technical discussions, code reviews, specifications, unit tests, and process improvements.
Requirements
MS in Computer Science or Electrical Engineering with at least 12 years of experience, or a PhD with at least 10 years of experience.
At least 10 years of EDA software development experience.
Strong knowledge of RTL/logic simulation, SDC constraints, timing analysis, and path exception handling in a static timing analysis tool.
Excellent C/C++ programming skills and a deep understanding of SystemVerilog or Verilog.
Experience with multithreaded and concurrent programming.
Ability to learn new technologies quickly and adapt to project requirements.
Collaborative environment focused on technical excellence and continuous learning.
Work with a geographically distributed team on semiconductor verification technology.
Paid vacation and paid holidays.
401(k) plan with employer match and employee stock purchase plan.
Medical, dental, and vision plan options.
Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →