Senior Signal Integrity Engineer (224G PAM4)

Location: Santa Clara, California; regular onsite presence required at the Bay Area office

Company

hirify.global develops next-generation switch platforms for large-scale AI deployments and datacenter networking.

What you will do

• Own signal integrity for one or more switch platforms from pre-layout feasibility and channel architecture through design release, EVT, DVT, and production debug.
• Set channel targets and loss budgets for 224G PAM4-per-lane links and align them with ASIC SerDes capability, module requirements, cost, and manufacturability constraints.
• Design and optimize ASIC BGA escapes, connector launches, vias, sequential lamination, backdrill strategies, and complete-channel behavior.
• Drive PCB stackup and material decisions with fabrication vendors, including laminate selection, Dk/Df modeling, impedance and loss coupons, and DFM closure.
• Run COM, ERL, IEEE 802.3dj, C2M, and C2C analysis, and correlate simulations with coupon data and measurements from VNA, TDR, high-speed scopes, BERT, and SerDes diagnostics.
• Improve SI methodology through Python automation, reusable analysis flows, routing and via rules, vendor collaboration, technical reviews, and mentoring of junior engineers.

Requirements

• MS or PhD in Electrical Engineering, Physics, or a related field; BS with equivalent depth considered.
• 10–15 years of signal integrity experience in high-speed system design and a track record of taking complex boards into production.
• Deep experience with 3D EM simulation and extraction using HFSS, SIwave, Sigrity, ADS, or equivalent, including correlation to measurements.
• Strong command of differential and mixed-mode S-parameters, mode conversion, crosstalk attribution, time-domain analysis, and link budgeting.
• Hands-on expertise in PCB stackups, low-loss materials, via and launch design, de-embedding, fixture design, and high-speed measurement.
• Strong Python skills for simulation automation and large-scale data analysis, plus the ability to communicate technical risks and provide actionable layout feedback.

Nice to have

• Experience with 224G PAM4 or 200G-per-lane channel design.
• Participation in IEEE 802.3 or OIF standards work.
• Experience with OSFP, QSFP-DD, DAC, ACC, AEC, LPO, or LRO module ecosystems.
• Power integrity or EMC expertise, or experience building an SI methodology or team at an early-stage organization.

Culture & Benefits

• Technical ownership of networking hardware used in large-scale AI deployments.
• Work on high-speed copper interconnect problems where established solutions may not yet exist.
• Collaboration with ASIC, connector, package, fabrication, layout, and hardware partners.
• Hands-on lab correlation and platform bring-up alongside engineers experienced in shipping datacenter networking hardware at scale.