Senior Engineer II - Design (ASIC/Verilog)

Location: Hauppauge, New York, United States; onsite

Company

hirify.global develops semiconductor products and connectivity solutions used in technologies around the world.

What you will do

• Design advanced connectivity devices for Ethernet, USB, PCIe, SerDes, and related interfaces.
• Contribute to the Networking and Communications Group Design Team.
• Develop digital designs using Verilog and SystemVerilog.
• Apply ASIC design and verification flows to production-oriented hardware projects.
• Support simulation, debugging, and FPGA emulation activities.

Requirements

• Bachelor’s degree in Electrical Engineering or an equivalent engineering discipline.
• 7+ years of relevant industry experience.
• Experience with Ethernet, USB, and/or PCIe.
• Proficiency in Verilog and SystemVerilog, including digital design project experience.
• Experience with ASIC design and/or verification flows, plus strong analytical, communication, documentation, debugging, and organizational skills.
• Ability to work effectively in a collaborative environment.

Nice to have

• Knowledge of USB 2.0, USB 3.0, USB Power Delivery, PCIe, Ethernet, and 1G–25G SerDes protocols.
• Experience with SPI, I2C, UART, or similar peripheral interfaces.
• Experience with simulation tools and Xilinx FPGA emulation and debugging.

Culture & Benefits

• Employee development programs supporting career growth.
• Values-driven culture focused on trust, empowerment, respect, diversity, and communication.
• Benefits and employee perks are available through Microchip’s careers program.
• Equal opportunity and affirmative action employment practices.