AI Lead Architect (Silicon Design Execution)

Location: San Jose, California, United States. Shift 1, United States of America. Applicants must be eligible for required U.S. export authorizations.

Salary: $206,400–$303,250 USD annually for the Bay Area California market, plus incentive opportunities.

Company

hirify.global designs and delivers FPGA and adaptive computing solutions for intelligent systems.

What you will do

• Define and own the AI/ML strategy for hardware design, verification, and implementation.
• Lead the full delivery path from opportunity identification and pilots to validation and production deployment.
• Build AI tooling including retrieval systems, agentic assistants, flow-debug and script-generation tools, and predictive models for quality of results and turnaround time.
• Establish evaluation, benchmarking, versioning, monitoring, and retirement practices for AI tools.
• Partner with CAD, IT, design, verification, DFT, implementation, and EDA teams to develop practical solutions and usable ML data foundations.
• Drive adoption, evaluate vendors, communicate impact to senior stakeholders and customers, and mentor engineering teams without direct management responsibility.

Requirements

• 12+ years of hands-on semiconductor or hardware design, verification, or implementation experience with deep familiarity with EDA tools and flows.
• Demonstrated experience applying AI/ML to real engineering workflows, preferably in chip design, verification, or physical implementation.
• Working proficiency in Python and modern ML/LLM tooling, with hands-on experience in fine-tuning, retrieval-augmented generation, agentic frameworks, or classical ML for EDA data.
• Experience leading technical initiatives and driving adoption across teams without direct management authority.
• Ability to engage senior customers and stakeholders in complex technical discussions, with strong written and verbal communication skills.
• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Eligibility for required U.S. export authorizations is required.

Nice to have

• Experience in an EDA, semiconductor, FPGA, or ASIC design environment.
• Experience with ML frameworks applied to placement, routing, timing, power, or verification coverage.
• Principal or Distinguished Engineer experience, or an equivalent senior individual-contributor level.
• Direct experience working with customers or external technical partners.

Culture & Benefits

• Incentive opportunities based on individual and company performance.
• Influence-driven role with no direct reports and cross-functional engineering collaboration.
• Work focused on modernizing hardware design through practical AI adoption.