Sr. Module Engineer (Hybrid Bonding)

Location: Santa Clara, CA, United States; onsite role with 10% travel

Salary: $147,000–$202,500 per year

Company

hirify.global develops materials science and engineering solutions for semiconductor chips, advanced displays, and next-generation electronics manufacturing.

What you will do

• Develop and optimize die-to-wafer hybrid bonding processes for advanced packaging applications.
• Establish process windows covering surface preparation, plasma activation, die placement, alignment, bonding conditions, and post-bond annealing.
• Integrate hybrid bonding into memory, chiplet, silicon interposer, system-on-wafer, and co-packaged optics platforms.
• Improve yield by addressing bond voids, die shift, overlay errors, non-uniform bonding, and particle contamination using DOE and statistical process control.
• Lead metrology, characterization, reliability testing, failure analysis, and qualification of bonding equipment and platforms.
• Lead cross-functional projects from concept through manufacturing transfer, publish technical results, present to leadership and customers, and mentor junior engineers.

Requirements

• Onsite work in Santa Clara, California, with 10% travel required.
• Master’s degree or Ph.D. in materials science, electrical engineering, mechanical engineering, chemical engineering, physics, or semiconductor manufacturing.
• At least 5 years of semiconductor process development experience after graduate school.
• Direct experience with hybrid bonding, thermocompression bonding, wafer bonding, advanced packaging, HBM, Cu interconnect technology, or chiplet integration.
• Knowledge of Cu-Cu interconnects, surface chemistry, plasma activation, CMP, planarization, defect engineering, process integration, and statistical process analysis.
• Experience with DOE, JMP or Minitab, metrology, and failure analysis techniques.

Nice to have

• Ph.D. with 5+ years of industry experience.
• Experience with HBM, 3D stacking, hybrid bonding equipment, direct bonding interconnect, die placement systems, or advanced packaging integration.
• Knowledge of AI/HPC packaging architectures and 200 mm or 300 mm wafer manufacturing.
• Patents, publications, or conference presentations in semiconductor packaging or related fields.

Culture & Benefits

• Supportive environment focused on learning, professional development, and technical innovation.
• Collaboration with R&D teams, equipment engineers, materials scientists, device architects, suppliers, and customers.
• Comprehensive benefits supporting employee health and wellbeing.
• Potential eligibility for bonus and stock award programs.