9 дней назад
Senior CPU Logic Design Engineer (SystemVerilog)
Мэтч & Сопровод
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Описание вакансии
Текст:
TL;DR
Senior CPU Logic Design Engineer (SystemVerilog): Developing complex allocation and resource-management mechanisms for Intel's high-performance CPU cores with an accent on micro-architecture, RTL implementation, and validation. Focus on leading features from architecture exploration through tape-in readiness, analyzing power-performance tradeoffs, and collaborating across architecture, verification, physical design, and post-silicon teams.
Location: Haifa, Israel. Hybrid work model with time split between the assigned site and off-site work; Shift 1 (Israel).
Company
's Core Engineering Group develops the Performance Core used across desktop, notebook, server, cloud CPU, and emerging AI products.
What you will do
- Define micro-architecture and develop RTL for complex allocation and resource-management mechanisms in high-performance CPU cores.
- Own features from architecture exploration through RTL development, validation support, debugging, and tape-in readiness.
- Lead significant design efforts and drive micro-architectural tradeoff discussions.
- Collaborate with architecture, verification, physical design, power-performance, and post-silicon teams.
- Contribute to CPU technologies focused on performance, power efficiency, scalability, and product competitiveness.
Requirements
- Bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related field.
- At least 5 years of experience in RTL logic design and development using SystemVerilog.
- Strong understanding of computer architecture, micro-architecture, and digital design principles.
- Experience defining and implementing complex micro-architectural features.
- Strong debugging, problem-solving, communication, and teamwork skills.
- Ability to independently drive features from definition through implementation and validation, including collaboration with architecture, validation, design, and post-silicon teams.
Nice to have
- Experience with design partitioning, micro-architectural tradeoff analysis, and functional validation or coverage planning.
- Experience with high-performance CPU or cache/memory subsystem designs.
- Experience with timing closure, power optimization, performance analysis, power-aware RTL coding, and power debugging.
- Familiarity with advanced design methodologies, scripting, automation, and geographically distributed engineering teams.
Culture & Benefits
- Hybrid work model combining on-site and off-site work.
- Cross-functional collaboration across architecture, verification, physical design, power-performance, and post-silicon engineering teams.
- Opportunity to contribute to next-generation CPU core technologies used across 's product portfolio.
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