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10 дней назад

Senior Design Verification Engineer (AI)

250 000$
Формат работы
remote (только USA)/onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior Design Verification Engineer (AI): Verifying complex IP, subsystems, and full-chip functionality for a next-generation AI accelerator with an accent on UVM-based environments, pre-silicon verification, and AI-assisted workflows. Focus on defining verification strategies across IP, SoC, and emulation environments, debugging complex designs, and driving functional coverage closure for first-pass silicon success.

Location: United States; remote work is available across Eastern and Central Time Zones, with onsite opportunities in the San Francisco Bay Area, Boulder, Virginia, San Mateo, and Mountain View.

Salary: Compensation varies by experience, technical expertise, and location; listed base salary ranges include $150,000–$190,000, $200,000–$300,000, $250,000–$400,000, and $250,000 base plus equity.

Company

hirify.global is partnering with a well-funded, early-stage AI hardware startup building an AI inference platform combining custom silicon, systems, and software.

What you will do

  • Own verification for a major functional area across IP, subsystem, SoC, and full-chip programs.
  • Define verification strategies, test plans, stimulus, and coverage models.
  • Develop reusable UVM-based verification environments and AI-assisted verification workflows.
  • Debug complex design issues and drive functional coverage closure with architecture, RTL, and software teams.
  • Improve verification methodologies for future silicon programs.

Requirements

  • 5+ years of hands-on pre-silicon verification experience on complex ASIC or SoC programs.
  • Experience with block or subsystem verification, CPU subsystems, IP integration, full-chip verification, hardware emulation, DMA, NoC, or die-to-die protocols.
  • Deep knowledge of UVM, constrained-random verification, and scalable testbench architecture.
  • Experience translating hardware and software specifications into verification strategies.
  • Ownership of verification planning through functional coverage closure and ability to deliver against aggressive schedules.
  • Strong collaboration skills in a fast-moving startup environment.

Nice to have

  • RISC-V architecture experience.
  • Formal verification experience.
  • Experience with Cadence Palladium, Siemens Veloce, or similar emulation platforms.
  • Post-silicon validation or bring-up experience.

Culture & Benefits

  • Work with an experienced engineering team from leading semiconductor and AI companies.
  • Medical, dental, and vision coverage.
  • 401(k) plan and generous paid time off.
  • Meaningful equity participation.

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