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11 дней назад

ASIC DFT Engineer

109 700 - 175 500$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
ASIC DFT Engineer (ASIC/DFT): Leading chip-level design-for-test programs from DFT specification through implementation, verification, silicon bring-up, and production release with an accent on scan, BIST, ATPG, test-vector generation, and yield improvement. Focus on debugging test flows and silicon failures, closing DFT timing with physical design teams, automating vector-generation flows, and developing testability solutions for 3nm and beyond.

Location: Fort Collins, Colorado, USA

Annual base salary: USD 109,700–175,500, plus discretionary bonus and equity opportunities.

Company

hirify.global develops ASIC and SoC products through its ASIC Product Division.

What you will do

  • Lead DFT programs from chip-level specification through implementation, verification, tape release, and production.
  • Implement and integrate Scan, MBIST, TAP, LBIST, IO, SerDes, and other DFT components.
  • Generate, verify, and debug ATPG patterns and test vectors before tape release and during silicon bring-up on ATE.
  • Collaborate with STA, physical design, test engineering, manufacturing, reliability, and operations teams on test closure and product quality.
  • Support silicon failure analysis, diagnostics, customer-returned part debugging, and yield improvement.
  • Automate DFT and test-vector generation flows and develop solutions for testability challenges in 3nm and beyond.

Requirements

  • Bachelor's degree with 8+ years of related experience, or a master's degree with 6+ years of related experience.
  • Strong DFT experience covering scan insertion and compression, ATPG, BIST, IO or analog DFT, and chip-level verification.
  • Experience with DFT Compiler, TestKompress, TetraMax or FastScan, Verilog, testbench development, and simulation.
  • Experience with MBIST for embedded memories and boundary scan verification using IEEE 1149.1 and IEEE 1149.6.
  • Knowledge of Test-STA, constraints, IEEE 1687, IJTAG, ICL, PDL, synthesis, transistor reliability, and semiconductor processing.
  • Strong debugging, root-cause analysis, communication, statistical process control, data analysis, and project management skills.

Nice to have

  • ATE experience and silicon debug involving SerDes, DDR, PCIe, Ethernet, CXL IOBIST, or Tessent SSN.

Culture & Benefits

  • Cross-functional collaboration with globally distributed customer, physical design, test engineering, and manufacturing stakeholders.
  • Medical, dental, and vision insurance.
  • 401(k) participation with company matching and an Employee Stock Purchase Program.
  • Paid holidays, sick leave, vacation time, and applicable family and other leave programs.
  • Discretionary annual bonus, new-hire equity grant, and annual equity awards.

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