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4 дня назад

ASIC DFT Engineer (ASIC/DFT)

121 900 - 195 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
ASIC DFT Engineer (ASIC/DFT): Leading chip-level DFT programs from architecture and implementation through verification, silicon bring-up, and production release with an accent on scan, BIST, ATPG, boundary scan, and test-vector automation. Focus on solving testability challenges in 3nm-and-beyond designs, closing DFT timing, debugging silicon and ATE failures, and improving yield.

Location: San Jose, California, USA

Annual base salary: USD 121,900–195,000

Company

hirify.global develops ASIC products through its ASIC Product Division.

What you will do

  • Lead DFT programs from chip-level specification through implementation, verification, tape release, and production.
  • Implement Scan, MBIST, TAP, LBIST, IO, SerDes, and other IP DFT integrations.
  • Generate, verify, debug, and validate test vectors during ATE and silicon bring-up.
  • Work with STA, physical design, test engineering, manufacturing, reliability, and customer teams on test closure and product requirements.
  • Support silicon failure analysis, diagnostics, customer-return debugging, and yield improvement.
  • Automate DFT and test-vector generation flows and develop solutions for 3nm-and-beyond testability challenges.

Requirements

  • Bachelor’s degree with 8+ years of related experience or a master’s degree with 6+ years of related experience.
  • Strong DFT experience with scan insertion and compression, ATPG, logic BIST, memory BIST, boundary scan, and test verification.
  • Experience with DFT Compiler, TestKompress, TetraMax, FastScan, Verilog, testbench generation, and simulation.
  • Knowledge of IEEE 1149.1, IEEE 1149.6, IEEE 1687, IJTAG, ICL, PDL, test-STA, and timing constraints.
  • Understanding of analog and digital circuit design, semiconductor processing, synthesis, transistor reliability, and statistical process control.
  • Strong debugging, root-cause analysis, communication, project management, and cross-functional collaboration skills.

Nice to have

  • ATE experience and SerDes, DDR, PCIe, Ethernet, CXL IOBIST, or Tessent SSN experience.

Culture & Benefits

  • Cross-functional collaboration with globally located engineering, customer, manufacturing, reliability, and operations teams.
  • Discretionary annual bonus and new-hire and annual equity awards.
  • Medical, dental, and vision coverage.
  • 401(k) participation with company matching and an employee stock purchase program.
  • Paid holidays, sick leave, vacation, family leave, and employee assistance support.

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