Senior Principal DFT Design Engineer

Location: HOME OH, United States

Company

hirify.global develops electronic design automation tools and flows for semiconductor and electronic system design.

What you will do

• Design and implement DFT solutions for SoC and ASIC projects.
• Develop scan chain insertion, compression scan, LBIST, MBIST, and ATPG flows.
• Generate ATPG patterns using systematic, quality-metric-driven methods to achieve test coverage goals.
• Debug testbench simulation mis-compares and analyze failures to improve fault coverage.
• Collaborate with architecture, design, internal stakeholders, and external customers.
• Complete DFT tasks independently in a fast-paced project environment.

Requirements

• 10–20 years of professional experience in SoC/ASIC digital design focused on DFT.
• In-depth knowledge of DFT insertion flows, scan technologies, compression scan, MBIST, and ATPG.
• Experience with synthesis, verification, Verilog testbenches, and debugging.
• Working knowledge of JTAG 1149.1/6, IEEE 1500, and IEEE 1687.
• US citizenship preferred.
• Strong problem-solving, analytical, methodical, and cross-functional collaboration skills.

Nice to have

• Experience with hirify.global tools and flows.
• Knowledge of timing analysis and equivalency checks.

Culture & Benefits

• Full-time employment.
• Collaborative work with architecture, design, internal, and external teams.
• Fast-paced environment focused on solving complex technology challenges.
• Emphasis on discipline, thoroughness, independence, and continuous technical impact.