Digital Design Manager (DFT)

Location: Toronto, Ontario, Canada

Salary: CAD $198,000–$220,000 per year, depending on experience, level, and business need. Discretionary bonus, incentives, and benefits may also apply.

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and software for CXL, Ethernet, NVLink, PCIe, and UALink technologies.

What you will do

• Lead DFT architecture and planning for high-speed PCIe and Ethernet signal-conditioning products and advanced multi-die packaging configurations.
• Develop test-access, coverage, observability, and diagnostic strategies for die-to-die interfaces, interposers, and package-level integration.
• Drive scan insertion, ATPG, compression, MBIST, LBIST, JTAG/IJTAG, and high-speed SerDes BIST requirements.
• Support tape-out, wafer sort, packaged-device testing, silicon bring-up, characterization, and production ramp.
• Collaborate with design, verification, physical design, packaging, product engineering, manufacturing, OSATs, and ATE vendors.
• Mentor DFT engineers and lead yield learning, failure analysis, diagnostics, and root-cause resolution.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 10–15 years of experience in digital design engineering or related semiconductor design and test work.
• Hands-on experience with scan, ATPG, compression, MBIST, LBIST, JTAG, and/or IJTAG methodologies.
• Understanding of the ASIC design flow from RTL through GDS and DFT signoff.
• Experience with DFT EDA tools such as Synopsys DFT Compiler, TetraMAX, DFTMAX, Siemens Tessent, or equivalent.
• Understanding of high-speed signal conditioning, SerDes physical-layer behavior, signal integrity, die-to-die connectivity, or advanced packaging test requirements.

Nice to have

• Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.
• Experience with 2.5D or 3D integration, silicon interposers, TSVs, hybrid bonding, micro-bumps, chiplets, or known-good-die strategies.
• Knowledge of IEEE 1838, IEEE 1149.1, IEEE 1687, and relevant JEDEC standards for multi-die testing.
• Experience with PCIe, Ethernet, UALink, high-speed SerDes validation, ATE platforms, wafer probe, OSAT engagement, production test economics, or yield analysis.

Culture & Benefits

• Opportunity to influence connectivity products for next-generation AI systems.
• Cross-functional collaboration across design, packaging, manufacturing, and test organizations.
• Discretionary bonus, incentives, and benefits may be available.
• Inclusive environment that encourages applications from people with diverse backgrounds and experiences.