Lead Software Engineer - Low Power Verification (AI)

Location: San Jose, California, United States

Annual salary: $114,800–$213,200 for California, plus potential bonus, equity, and benefits.

Company

hirify.global develops technology for electronic design, emulation, prototyping, and verification.

What you will do

• Enhance UPF debug performance and usability across Parallel Partition Compiler and Modular Compiler flows, including Dielet UPF support.
• Scale UPF event logging and violation detection for multi-billion-gate low-power designs.
• Rebuild UPF documentation around end-to-end debug scenarios using valid SystemVerilog and UPF examples.
• Develop AI-assisted UPF debug tools to reduce time to root cause.
• Collaborate with R&D, PE, and AE teams to deploy UPF solutions across AVIP, UVMA, MC, and Dielet flows.
• Help consolidate and unify UPF debugging across Palladium and Protium.

Requirements

• BS in Computer Science, Electrical Engineering, or a related field with 4+ years of experience; MS with 2+ years; PhD with 1+ year; or equivalent practical experience.
• Working knowledge of IEEE 1801 UPF and RTL languages including Verilog, SystemVerilog, and VHDL.
• Strong debugging and root-cause analysis skills using logs, waveforms, traces, test cases, and user reports.
• Ability to read, review, and reason about C++ code and object-oriented designs.
• Fluency with AI-assisted coding tools such as Copilot, Claude, Cursor, or equivalent, including critical evaluation of generated output.
• Strong communication and technical writing skills for creating clear, user-facing workflows.

Culture & Benefits

• Paid vacation and holidays.
• 401(k) plan with employer match.
• Employee stock purchase plan.
• Medical, dental, and vision plan options.
• Potential bonus and equity compensation.