Senior Principal Engineer (FPGA)

Location: San Jose, California, United States; additional remote location in Colorado, United States. Applicants must be eligible for required U.S. export authorizations.

Salary: $231.5K–$304.5K USD annually for the Bay Area, California.

Company

hirify.global develops FPGA software and implementation technologies for programmable computing and semiconductor design automation.

What you will do

• Define the architectural roadmap for FPGA compiler technologies.
• Design optimization algorithms for timing closure, area reduction, power optimization, routability, and runtime improvement.
• Lead timing-driven optimization methodologies and scalable implementation solutions for large hierarchical designs.
• Drive innovation across synthesis, placement, routing, timing analysis, and physical optimization.
• Analyze customer workloads and field feedback, and lead investigations of complex timing and implementation problems.
• Mentor engineers, influence technical direction, and collaborate with product management and strategic customers.

Requirements

• BS, MS, or PhD in Electrical Engineering, Computer Science, Computer Engineering, or a related field.
• 15+ years of experience developing EDA software, FPGA tools, ASIC implementation tools, or related optimization technologies.
• Deep expertise in physical synthesis, timing analysis, logic synthesis, placement and routing, design optimization, FPGA architecture, CAD flows, or physical design implementation.
• Experience architecting large-scale software systems and optimization engines.
• Strong C++, data structures, algorithms, and performance optimization skills.
• Eligibility for required U.S. export authorizations is required.

Nice to have

• Experience developing commercial FPGA or ASIC implementation tools.
• Expertise in path-based optimization, timing-driven synthesis, or physical design methodologies.
• Experience improving quality of results, runtime performance, or scalability for large customer designs.
• Machine learning applications for EDA optimization and implementation flows.
• Patents, significant technical publications, or experience as a Distinguished Engineer, Architect, Fellow, or equivalent technical leader.

Culture & Benefits

• Work alongside engineers solving complex semiconductor design automation problems.
• Influence the technical direction of FPGA implementation technologies and software platforms.
• Incentive opportunities based on individual and company performance.
• Regular full-time employment.