Principal AMS Engineer (AMS/PHY)

Location: Taiwan

Company

hirify.global is a stealth-mode startup building foundational technology for performance, scalability, and resiliency in large-scale AI data center clusters.

What you will do

• Architect and develop analog and mixed-signal circuits and subsystems for high-speed interfaces and SoCs.
• Lead high-speed PHY architecture and integration for die-to-die, UCIe-class, DDR, HBM, SerDes, and related interfaces.
• Develop AMS functions including clocking, PLL/DLL-related circuits, references, voltage monitoring, calibration, and data-path circuitry.
• Drive chip, package, and PCB co-design for signal and power integrity, timing, low-power design, and system-level analysis.
• Lead AMS integration into complex SoCs and collaborate with digital, verification, physical design, package, systems, and software teams.
• Drive designs from architecture and verification through tapeout, bring-up, characterization, post-silicon validation, and production.

Requirements

• Master’s degree or Ph.D. in Electrical Engineering, Electronics Engineering, Microelectronics, or a related field, or equivalent practical experience.
• Deep experience in analog and mixed-signal IC design and implementation.
• Strong experience with high-speed PHY architecture and design, including interfaces such as DDR, HBM, die-to-die, UCIe, SerDes, or MIPI.
• Experience with analog IP such as PLLs/DLLs, clocking circuits, voltage and reference circuits, ADCs/DACs, LDOs, and IO.
• Strong understanding of SoC integration, timing and STA, low-power design, UPF, IO integration, physical design interaction, and floorplanning.
• Experience taking complex silicon designs from architecture through tapeout and post-silicon validation, with the ability to lead ambiguous cross-functional problems.

Nice to have

• Direct experience with UCIe or proprietary die-to-die interfaces.
• Experience with advanced packaging, chiplets, multi-die systems, or complete PHY subsystems.
• Background in IO/ESD and latch-up design, analog timing characterization, or design-flow and CAD infrastructure.
• Experience leading third-party IP and design-service vendors or building new design teams and flows.

Culture & Benefits

• Work alongside experienced builders and operators with a strong focus on trust, integrity, respect, and shared responsibility.
• Meaningful technical work on foundational infrastructure for large-scale AI data centers.
• Competitive compensation aligned with senior engineering roles in Taiwan; exact compensation depends on experience and location.
• Equal opportunity employment based on merit and business needs.