Senior I/O Chiplet RTL Design Engineer

Location: Ottawa, Canada preferred; hybrid arrangements may be considered based on the candidate and project needs

Company

hirify.global supports ASIC and FPGA design, verification, and embedded software projects across Canada and internationally.

What you will do

• Translate architectural requirements into synthesizable SystemVerilog and Verilog, owning assigned blocks through front-end sign-off.
• Define micro-architectures, interfaces, latency, throughput, and resource budgets for configurable switching fabrics, protocol multiplexers, pipelined datapaths, and rate-adaptation logic.
• Integrate protocol and PHY IP, including clocking, reset, status, control interfaces, and high-speed interfaces such as UCIe, PCIe, and Ethernet.
• Implement CSR access, configuration sequencing, interrupts, embedded management logic, low-power controls, and related power-intent checks.
• Develop assertions and resolve lint, CDC, RDC, connectivity, synthesis, and timing findings.
• Collaborate with architecture, verification, firmware, physical design, and IP partners on debugging, partitioning, congestion, timing closure, DFT, formal equivalence, and RTL handoffs.

Requirements

• At least 10 years of hands-on ASIC RTL design experience with ownership through successful tape-out.
• Strong SystemVerilog and Verilog skills, including specification-driven RTL development.
• Experience with high-bandwidth datapaths, pipelining, multiplexing, multi-clock design, and complex IP integration.
• Practical experience with at least one high-speed interface such as PCIe, Ethernet, or die-to-die interconnect.
• Strong knowledge of CDC, RDC, reset sequencing, assertions, static design checks, synthesis, timing constraints, and timing-report analysis.
• Scripting experience in Python, Tcl, or similar languages, plus the ability to lead design reviews and communicate technical risks clearly.

Nice to have

• UCIe or other chiplet interconnect experience, including protocol-to-PHY integration and advanced packaging constraints.
• PCIe Gen6/Gen7, 200G Ethernet, or 224G PAM4 SerDes integration experience.
• Advanced-node ASIC delivery, UPF-based low-power design, or physically aware RTL partitioning.
• Embedded RISC-V subsystems, AXI/APB, secure boot, sideband management, or FPGA prototyping experience.

Culture & Benefits

• Direct technical ownership with access to architects and implementation specialists.
• Collaboration with distributed engineering teams.
• Work on connectivity challenges for advanced AI and computing systems.
• Opportunity to develop reusable engineering methods for future chiplet programs.
• Emphasis on sound engineering judgment, collaboration, and sustainable work-life balance.

Hiring process

• Detailed client and program information is shared confidentially during interviews.
• Compensation is discussed during the recruitment process and reflects experience, technical capability, and role responsibilities.