System Technology Research Engineer (PhD Intern) (Semiconductor Packaging)

Location: Hybrid role based at an hirify.global site in Hillsboro, Oregon, with additional locations in Santa Clara, California, and Austin, Texas, USA

Annual salary range: $141,998–$142,002 USD

Company

hirify.global's Foundry System Technology team advances semiconductor and packaging manufacturing technologies, System Technology Co-optimisation, and hirify.global's semiconductor processing and packaging roadmap.

What you will do

• Develop and enhance System Technology Co-optimisation methodologies.
• Evaluate 3D and 2.5D dis-aggregation schemes for memory and logic stacking.
• Assess solder microbump and hybrid-bonding approaches across product architectures.
• Perform system-level evaluations of devices, interconnects, patterning, materials, systems, and integration schemes.
• Collaborate with cross-functional teams on semiconductor processing and packaging innovation.

Requirements

• Active Ph.D. candidacy in Electrical Engineering, Electronics Engineering, Computer Architecture and Design, or a similar field.
• 1–2+ years of relevant research experience in system architecture modeling, digital circuit analysis and design, VLSI physical layout, electronic design automation, or multiphysics modeling.
• Familiarity with IC design and physical-layout tools such as Cadence Virtuoso or Synopsys Fusion Compiler.
• Analytical, problem-solving, communication, collaboration, prioritization, and time-management skills.

Nice to have

• System architecture design and modeling experience.
• IC design, simulation, physical layout, and tapeout experience.
• DRAM and SRAM circuit design and layout knowledge.
• Integrated-circuit manufacturing-flow and 2.5D/3D packaging knowledge.
• 3DIC design and simulation experience and strong Python programming skills.

Culture & Benefits

• Full-time student internship lasting at least three months during summer 2026, with possible extension.
• Hybrid work model combining on-site work at an assigned hirify.global site with off-site work.
• Hands-on experience with semiconductor processing, packaging, and other advanced technologies.
• Competitive compensation with stock bonuses, health, retirement, and vacation benefits.
• Opportunity to collaborate with industry leaders and contribute to semiconductor technology development.