Senior Reliability PDK and TFM Engineer

Location: Hybrid role based at an Intel site in the United States. Primary location: Hillsboro, Oregon. Additional locations: Phoenix, Arizona; Folsom and Santa Clara, California.

Annual salary: $149,600–$284,580 USD.

Company

Intel develops semiconductor technologies, design enablement platforms, and products spanning AI, analytics, and cloud-to-edge computing.

What you will do

• Define and generate reliability-focused PDK design rules and collateral covering reliability mechanisms, quality assurance, and benchmarking.
• Enable EDA tools and design flows in partnership with PDK development teams and EDA vendors.
• Develop technology flow and methodology solutions for design reliability verification.
• Perform competitive analysis and benchmark technology reliability.
• Deliver PDKs, design rules, collateral, TFM, and IP ecosystem capabilities for internal and external customer designs.

Requirements

• Bachelor’s degree in electrical engineering, physics, or a related field with 6+ years of relevant experience; alternatively, a master’s degree with 4+ years or a PhD with 2+ years of relevant experience.
• At least 3 years of experience in PDK development, reliability tools and flows, design for reliability, circuit/IP/SoC reliability validation, or EDA tool and flow development.
• Experience with PDK development and validation, reliability design rules, techfile generation, and quality assurance.
• Knowledge of reliability verification and physics, including BTI, HCI, electromigration, high-voltage design, EOS, and ESD.
• Strong communication, presentation, program management, stakeholder management, teamwork, and quality-focused problem-solving skills.
• Ability to work in a hybrid model from an assigned United States Intel site.

Nice to have

• Master’s or PhD degree in electrical engineering, physics, or a related field.
• Experience applying AI or programming to create code, agents, or scripts for design-rule generation, techfile generation, and quality assurance.
• Experience with IP and SoC design validation, sign-off, design impact analysis, and risk assessment.

Culture & Benefits

• Hybrid work model combining on-site and off-site work.
• Health, dental, retirement, vacation, and paid holiday benefits.
• Three weeks of paid vacation and 14 paid holidays per year.
• Four-week paid sabbatical every four years of employment.
• Performance-based bonuses, stock-related compensation, and an employee stock purchase program.