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10 часов назад

Product Development/DFX Lead - Neuromorphic Computing

141 910 - 269 100$
Формат работы
hybrid
Тип работы
fulltime
Грейд
lead
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Product Development/DFX Lead - Neuromorphic Computing (DFT/DFX): Architecting and driving SoC-level test, debug, reliability, and manufacturing-readiness solutions for Intel's neuromorphic silicon program with an accent on scan insertion, compression, ATPG, and asynchronous circuit testing. Focus on building scalable pre-silicon test-vector frameworks, enabling silicon power-on, debugging failures, and developing new DFX methodologies for high-volume production.

Location: Hybrid role based at an hirify.global site in the United States, with primary location in Hillsboro, Oregon and additional locations in Phoenix, Arizona; Folsom and Santa Clara, California; and Austin, Texas.

Annual salary: $141,910–$269,100 USD, depending on work location, skills, experience, and education.

Company

hirify.global develops semiconductor technologies and neuromorphic computing architectures for physical AI systems.

What you will do

  • Architect the complete SoC-level DFT solution for synchronous and asynchronous designs.
  • Lead scan-insertion and compression flow development at partition and SoC levels.
  • Build scalable frameworks across EDA tools, RTL, and emulation models to generate and validate test vectors before silicon.
  • Collaborate with design teams on DFT, DFD, and DFM features that support manufacturing readiness and high-volume production.
  • Lead silicon power-on, enable tester content, debug failures, and maintain developed tools and flows.

Requirements

  • Bachelor's degree with 6+ years of hands-on DFT experience, or a master's degree with 4+ years of experience, covering architecture through silicon bring-up.
  • 6+ years of experience architecting the DFT stack, including scan insertion, compression, and ATPG vector generation.
  • 4+ years of direct ownership of IP- and SoC-level scan constructs such as boundary scan, JTAG, TAP, BIST, and MBIST.
  • At least 1 year of post-silicon debugging experience and driving circuit changes for testability and reliability improvements.
  • Strong SystemVerilog, SystemC, and object-oriented programming experience with pre-silicon verification.
  • Ability to work in a hybrid model at an assigned hirify.global site in the United States.

Nice to have

  • Experience with custom ASICs or AI/ML accelerator design.
  • Experience with post-silicon bin split, die-level cherry picking, and fault grading.
  • Experience reducing test time on automatic test equipment.
  • Experience with asynchronous architectures and circuits.
  • At least 1 year of experience using AI tools to set up tool flows, debug issues, and improve productivity.

Culture & Benefits

  • Hybrid work model combining on-site and off-site work.
  • Competitive pay with stock bonuses.
  • Health, retirement, and vacation benefits.
  • Work on neuromorphic computing technologies developed with a global ecosystem of research groups.

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