Hardware Design Integrity Engineer (Networking)

Location: Santa Clara, California, USA

Salary: $130,000–$225,000 base pay per year, with potential bonuses and equity.

Company

hirify.global develops client-to-cloud networking solutions for data centers, campuses, routing environments, and AI clusters.

What you will do

• Debug production issues in high-speed networking and Ethernet hardware and deliver corrective solutions.
• Investigate CPU/ASIC, power, signal integrity, clocking, PCIe, optics, fabrication, and component-level issues.
• Handle field escalations with software and customer teams by analyzing logs, identifying bugs, and minimizing service interruption.
• Write scripts for log analysis and live debug sessions.
• Perform lab measurements and debug hardware, firmware, schematics, bills of materials, and fabrication changes.
• Identify test escapes, improve validation coverage, and present root cause analyses to executives and customers.

Requirements

• BSEE or MSEE.
• 5+ years of relevant hardware engineering experience.
• Experience debugging networking hardware and designing 20+ layer boards with 50G+ signals.
• Experience debugging and validating multi-phase DC/DC converters for high-current, high-transient loads.
• Experience with high-speed interfaces such as DDR and PCIe, plus low-speed signals including I2C and SPI.
• Knowledge of signal and power integrity tools and concepts, including PDN, Bode plots, PCIe analyzers, TDRs, and VNAs; FPGA design using Verilog.

Culture & Benefits

• Cross-functional collaboration with software, product management, manufacturing, component, failure-analysis, ODM, and customer teams.
• Work on networking products used in enterprise campuses, hyperscaler data centers, and AI clusters.
• US-based employees receive medical, dental, vision, wellbeing, tax savings, and income protection benefits.
• Additional compensation may include discretionary bonuses and equity.