Junior Verification Engineer (SystemVerilog/UVM)

Location: Jerusalem, Haifa, or Tel Aviv, Israel

Company

hirify.global develops high-speed silicon and SerDes IP for digital and analog systems, DSP pipelines, and firmware-hardware co-verification.

What you will do

• Perform constrained-random and coverage-driven verification of complex high-speed SerDes mixed-signal IP.
• Develop advanced verification environments for silicon designs operating at 10Gbps to 100Gbps+.
• Validate DSP datapaths and verify firmware-hardware interactions.
• Support the full verification lifecycle from specification through tape-out sign-off.
• Use AI-assisted tools as part of the daily engineering workflow.

Requirements

• Bachelor's degree in electrical engineering, computer engineering, or computer science.
• 0–3 years of industry or academic experience in hardware design or verification.
• Strong understanding of digital design, computer architecture, and software programming.
• Analytical approach to root-cause analysis and problem solving.
• Ability to work in a dynamic, multidisciplinary environment.

Nice to have

• Hands-on experience with SystemVerilog and UVM.
• Python scripting for verification automation.
• Familiarity with mixed-signal or analog simulation concepts.
• Knowledge of high-speed protocols such as PCIe or Ethernet.
• Internship or previous experience in RTL design or verification.

Culture & Benefits

• Collaborative and innovative engineering environment where ideas are encouraged at every level.
• Exposure to the complete verification lifecycle.
• Modern engineering tooling, including AI-assisted development.
• Clear growth path from the beginning of the role.
• Full-time regular employment.