12 дней назад
Senior Mixed-Signal Verification Engineer (SystemVerilog)
Мэтч & Сопровод
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Описание вакансии
Текст:
TL;DR
Senior Mixed-Signal Verification Engineer (SystemVerilog/mixed-signal SoCs): Owning verification methodology, planning, and execution for digital-to-analog interfaces in Arago's Systems-on-Chip with an accent on verification environments, behavioral modeling, and cross-functional integration. Focus on developing tests, assertions, scoreboards, and coverage, debugging RTL and analog behavior, and driving complex interface verification to sign-off.
Location: On-site in Paris or Tel Aviv
Company
develops proprietary processors that fuse optical and CMOS technologies to improve computing performance for AI workloads.
What you will do
- Own the mixed-signal verification methodology and verification plan for digital-to-analog interfaces on SoCs.
- Build and maintain verification environments at block, subsystem, and SoC levels.
- Develop tests, assertions, checkers, scoreboards, and functional coverage.
- Verify digital control and configuration of analog and mixed-signal circuitry across normal operation, corner cases, and error conditions.
- Run regressions, analyze coverage, debug failures, and drive verification to sign-off.
- Develop or integrate behavioral and real-number models and collaborate with analog, RTL, architecture, firmware, and SoC verification teams.
Requirements
- Strong hands-on experience in ASIC or SoC verification.
- Experience verifying mixed-signal blocks or digital-to-analog and analog-to-digital interfaces.
- Strong SystemVerilog skills and practical experience with UVM or an equivalent methodology.
- Experience building verification environments and developing tests, assertions, scoreboards, and functional coverage.
- Understanding of digital design fundamentals and basic analog/mixed-signal concepts, with strong debugging skills across RTL, models, clocks, resets, configuration, and analog behavior.
- Proficient English required.
Nice to have
- Verification experience with PCIe, DDR/LPDDR, UCIe, SerDes, USB, CXL, or similar high-speed interface IP.
- Experience with interface initialization, link training, calibration, adaptation, clocking, power-state transitions, or digital/analog control loops.
- Experience with real-number modeling, SystemVerilog RNM, wreal, Verilog-AMS, behavioral analog/PHY models, low-power verification, or UPF.
- Experience driving complex IP or SoC verification through coverage closure and tape-out.
Culture & Benefits
- Competitive cash compensation based on location, experience, and internal pay levels.
- Meaningful stock option plan included in the majority of full-time offers.
- Healthcare coverage, including family-friendly options, and pension contributions.
- Professional development support and 25 days of paid time off in addition to public holidays.
- Ownership of a key technical domain with opportunities for vertical and horizontal growth.
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