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10 дней назад

Analog Layout Intern (CMOS)

Формат работы
onsite
Тип работы
fulltime
Грейд
trainee
Английский
c1
Страна
Italy
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Analog Layout Intern (CMOS): Learning and developing analog integrated-circuit layouts using advanced CAD and physical verification tools with an accent on CMOS design rules, parasitic optimization, and layout verification. Focus on running DRC/LVS checks, analyzing EMIR concepts, optimizing area and parasitic resistance and capacitance, and presenting progress to technical teams.

Location: Pavia, Italy; the internship takes place in the Pavia office

Company

hirify.global develops semiconductor solutions and integrated-circuit technologies for enterprise, cloud, AI, storage, security, networking, and carrier infrastructure.

What you will do

  • Learn and use IC layout development CAD and physical verification tools.
  • Train in mask and layout design using Cadence Virtuoso EXL, Custom Compiler, and Synopsys tools.
  • Apply design rules for advanced CMOS technology nodes from 16nm to 3nm.
  • Run DRC and LVS checks and learn EMIR concepts for analog IC layout.
  • Optimize layouts for area and parasitic resistance and capacitance.
  • Collaborate with the analog, layout, and project teams, attend mentoring meetings, provide status updates, and present issues or solutions.

Requirements

  • Student of Electronics or a similar technical field at an accredited Italian university, or a Bachelor’s/Master’s graduate.
  • Fundamental understanding of electronics and circuit elements including diodes, transistors, capacitors, and resistors.
  • Basic digital knowledge of latches, flip-flops, and combinatorial logic.
  • Strong communication skills for status updates and presentations to global teams across different time zones.
  • Fluent English and sufficient Italian are required.
  • Must be eligible to work in Italy without restrictions.

Nice to have

  • Coursework or additional training in analog design or layout.

Culture & Benefits

  • Internship duration of up to six months with exposure to a range of IC design engineering skills and tools.
  • Regular meetings with a technical mentor and collaboration with layout and project teams.
  • Collaborative, transparent, and inclusive work environment.
  • Opportunities to learn advanced technologies and develop engineering skills.
  • Eligible for bonus and equity plans, including a new-hire equity grant and annual equity refreshers.

Hiring process

  • Interviews evaluate individual experience, thought process, and communication skills in real time.
  • AI tools, transcription apps, automated note-taking bots, and real-time answer generators are not permitted during interviews.
  • The role may require an export license review before employment because of U.S. export control requirements.

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