Sr. Staff Engineer, Front-End Verification (RISC-V)

Location: Hybrid, based in Austin, Texas, or Santa Clara, California, United States

Salary: $100,000–$500,000, including base and variable compensation targets. Actual compensation depends on experience, skills, education, background, and location.

Company

Tenstorrent develops high-performance AI computing technologies spanning software models, compilers, platforms, networking, semiconductors, and RISC-V CPUs.

What you will do

• Build and maintain UVM testbenches for instruction fetch units, branch predictors, and related CPU front-end blocks.
• Develop constrained-random and directed tests for speculation depth, misprediction and redirect flows, fetch bubbles, and cache/TLB interactions.
• Develop and maintain C++ reference models and predictors for cycle-accurate or transaction-level checking.
• Build reusable transactors, predictors, scoreboards, stimulus generators, and checkers.
• Execute verification plans, track functional and code coverage, and verify microarchitectural edge cases.
• Collaborate with RTL, performance modeling, and software teams to identify and resolve misspeculation, redirect, and fetch bugs.

Requirements

• Solid experience verifying CPU front-end blocks such as instruction fetch, branch predictors, instruction caches/TLBs, or decode.
• Experience with SystemVerilog, UVM, and C++.
• Hands-on experience building clean, controllable unit-level verification environments with precise stimulus and checking.
• Experience creating reusable transactors, predictors, and scoreboards across verification levels.
• Ability to work directly with RTL designers to trace and fix complex fetch-related bugs.
• Must be eligible to access U.S. export-controlled technology; employment may depend on citizenship, permanent residency, or prior U.S. government license approval.

Nice to have

• Experience with industry-standard simulators and open-source flows such as Verilator.
• Experience across simulation and emulation environments.
• Exposure to high-performance RISC-V fetch pipelines and prediction structures.

Culture & Benefits

• Competitive compensation package and benefits.
• Collaborative environment focused on curiosity and solving difficult technical problems.
• Opportunity to work with RTL, performance modeling, and software teams.
• Experience with maintainable design-verification infrastructure and evolving hardware designs.