Senior SoC Design Engineer (ASIC/RTL)

Location: Burnaby, British Columbia, Canada

Annual base salary: $86,000–$186,000 USD

Company

hirify.global is a large semiconductor company developing products for data centers, servers, storage systems, and other computing applications.

What you will do

• Design complex digital integrated circuits at block, subsystem, and device level, ranging from 100K to 50M+ gates.
• Define subsystem and block features and document design, implementation, and register details.
• Support emulation and ASIC lab validation, including debugging, logic modifications, and workarounds.
• Collaborate with design and verification teams across multiple locations to resolve technical issues and communicate status.
• Present design implementation decisions and trade-offs to architects.
• Read and apply storage and computer interface protocol standards.

Requirements

• Bachelor’s or master’s degree in electrical engineering, computer engineering, or an equivalent field.
• 3–5 years of related experience.
• Required experience designing RTL with SystemVerilog and Verilog.
• Experience with complex ASIC design flows, including simulation, debug, logic synthesis, static timing analysis, layout, and revision control.
• Knowledge of design and verification tools such as Synopsys Design Compiler, Cadence Incisive, and waveform viewers.
• Strong analytical, debugging, teamwork, communication, and time-management skills.

Nice to have

• Formal verification experience.
• Scripting or programming experience with C shell, Bash, Perl, Python, or Tcl.
• PCI Express, AHB, or AXI protocol knowledge.
• Experience with physical design teams, low-power methodology, and layout implementation.

Culture & Benefits

• Full-time position within the Data Center Solutions business unit.
• Health benefits begin on the first day.
• Compensation includes base pay, restricted stock units, and quarterly bonuses.
• Retirement savings plans and an employee stock purchase program are available.
• Travel requirement is 0%–25%.