7 дней назад
TOP Design Verification Engineer Intern
35 - 45$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
TOP Design Verification Engineer Intern (SystemVerilog/UVM): Testing SOC TOP microarchitecture by defining verification requirements, modifying test benches, creating test cases, and debugging design issues with an accent on functional and toggle coverage. Focus on building verification environments, identifying failures, filing bug reports, and validating SOC functionality across Windows and Linux.
Location: San Jose, United States; onsite
Salary: $35–$45 per hour
Company
develops DRAM and NAND flash memory solutions for smartphones, data centers, cloud computing, and advanced electronic devices.
What you will do
- Study SOC TOP microarchitecture and define verification requirements.
- Modify test benches for SOC TOP-level testing.
- Create and modify test cases to validate SOC functionality.
- Debug issues and file bug reports for designers.
- Test against functional and toggle coverage criteria.
Requirements
- Bachelor’s or master’s degree in electrical engineering or a related field.
- Experience with digital IC design and verification.
- Experience working in Windows and Linux environments.
- Scripting experience with Python or Perl.
- Experience with SystemVerilog, UVM, and C or assembly coding.
- Experience with Perforce and Confluence.
Nice to have
- Familiarity with UCIe, CPU architecture, NAND protocols, and AI productivity tools.
Culture & Benefits
- Six-month internship.
- 40 hours per week.
- Start date: immediately, with availability indicated for September or October 2026.
- Opportunity to contribute to semiconductor innovation and advanced memory technologies.
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