6 дней назад
Principal Design Verification Engineer (GPU)
250 000 - 280 000$
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Описание вакансии
Текст:
TL;DR
Principal Design Verification Engineer (GPU): Owning verification strategy and execution for complex graphics processor IPs and full-chip SoCs with an accent on UVM environments, coverage closure, low-power verification, and gate-level simulation. Focus on leading verification teams, solving timing-aware and cross-domain debug challenges, and delivering high-quality silicon through signoff and post-silicon bring-up.
Location: Sunnyvale, California, United States. On-site five days per week; no hybrid option.
Salary: $250,000–$280,000 per year base pay for the role based in California.
Company
is a semiconductor startup building high-performance, efficient graphics processors for immersive content creation, simulation, and consumption.
What you will do
- Own end-to-end verification strategy from block and subsystem levels through full-chip SoC verification.
- Build, mentor, and scale a verification team while defining plans, milestones, and coverage goals.
- Lead UVM-based environments, testbench architecture, stimulus strategy, reusable components, regressions, and signoff.
- Drive functional, code, and assertion coverage closure, including formal verification, linting, and CDC/RDC analysis.
- Lead gate-level simulation with SDF annotation, timing-aware debug, low-power verification, and power-aware simulation.
- Collaborate with architecture, RTL, physical design, customers, and partners on verification readiness, post-silicon bring-up, and debug.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering or a related field.
- 12–15 years of ASIC/SoC design verification experience and a record of leading teams and delivering multiple tapeouts.
- Strong expertise in SystemVerilog, UVM, functional coverage, SVA assertions, constrained-random verification, and complex SoC-level debugging.
- Hands-on experience with Synopsys VCS, Cadence Xcelium, and Synopsys Verdi.
- Strong understanding of clock/reset domain crossings, low-power verification, gate-level simulation, and SDF annotation.
- Must work on-site in the Sunnyvale office five days per week.
Nice to have
- Experience with CPU, GPU, AI, or networking SoCs.
- Expertise in GLS debug, including X-propagation, SDF issues, and timing failures.
- Familiarity with emulation platforms such as Synopsys ZeBu.
- Post-silicon validation and bring-up experience, plus performance or system-level validation knowledge.
- Strong Python or TCL scripting skills for automation and regression scaling.
Culture & Benefits
- First-principles approach focused on reducing barriers to immersive content creation and consumption.
- Culture built around being fearless, remaining adaptable, and educating the ego through collaboration.
- Medical, dental, and vision premiums fully covered.
- Stock options and a 401(k) match.
- Work-from-home hardware provided, while this role remains fully on-site.
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