Senior FPGA IP Solution Design Engineer

Location: Penang, Malaysia

Company

hirify.global develops intellectual property cores optimized for FPGA devices, focusing on performance, cost efficiency, ease of use, and time-to-market.

What you will do

• Design and develop wireless FPGA soft IP cores using Verilog and SystemVerilog RTL.
• Participate in high-level product specifications and FPGA IP system and solution engineering.
• Verify RTL designs using simulation and verification tools.
• Prototype IP through FPGA emulation and perform hardware validation.
• Collaborate with system architects, verification engineers, and software teams to deliver reliable, high-performance wireless solutions.

Requirements

• Bachelor's degree in Electrical, Electronics, Computer Engineering, or an equivalent field.
• Proficiency in Verilog/SystemVerilog and RTL design coding.
• Experience with FPGA, custom IC, or ASIC design across architecture, design, validation, or product development.
• Understanding of timing closure, clock domain crossing, and FPGA constraints.
• Familiarity with simulation and verification tools such as Synopsys VCS, Questa, or ModelSim.
• Strong analytical, problem-solving, written, and verbal communication skills.

Nice to have

• Knowledge of high-speed serial interfaces such as Ethernet, CPRI, and eCPRI.
• Familiarity with O-RAN architectures.
• Experience with Perl, TCL, Python, and shell scripting.

Culture & Benefits

• Regular full-time employment.
• Shift 1 working schedule aligned with Malaysia.
• Cross-functional collaboration focused on accountability, integrity, innovation, and teamwork.