Staff IP Design Engineer (FPGA)

Location: Penang, Malaysia; right to work in Malaysia required

Company

hirify.global develops low-cost, low-power programmable logic solutions, including FPGA, CPLD, and programmable power management devices.

What you will do

• Build connectivity IP portfolios for Lattice FPGAs.
• Translate specifications into high-speed RTL designs in collaboration with architects.
• Optimize designs for performance, power, and logic utilization.
• Perform FPGA logic verification, debugging, and timing closure.
• Develop soft IP packages, example designs, and testbenches.
• Support hardware validation and interoperability testing while enabling the team to deliver projects.

Requirements

• BS, MS, or PhD in Electronics or Computer Engineering.
• At least 8 years of FPGA or system design experience.
• Hands-on experience with FPGA RTL design, logic verification, debugging, and timing closure.
• Programming experience with C, C++, Perl, TCL, or Python.
• Technical leadership, problem-solving, communication, and independent execution skills.
• Must provide satisfactory proof of the right to work in Malaysia.

Nice to have

• Experience with high-speed SERDES and video protocols such as DisplayPort, HDMI, MIPI, or SDI.
• Experience with SPI, I2C, or I3C peripherals.
• Hardware validation or hardware interoperability testing experience.
• Experience with soft IP packaging, example design, and testbench development.

Culture & Benefits

• Fast-paced, results-oriented environment focused on R&D, product innovation, and customer service.
• Collaborative team-first organization working with diverse engineers and international teams.
• Comprehensive compensation and benefits program.
• Work in a global programmable logic technology organization of approximately 1,000 employees.