Design Eng 2 (SystemVerilog)

Location: Manila, Philippines. Proof of the right to work in the Philippines is required.

Company

hirify.global develops low-cost, low-power programmable logic solutions, including FPGA, CPLD, and programmable power management devices.

What you will do

• Develop verification plans, define clear metrics, and track progress throughout the project.
• Verify design blocks, subsystems, and full-chip implementations using assertion-based, formal, directed, and randomized testing.
• Develop SystemVerilog and C-based UVM testbenches, including verification components, BFMs, and related tools.
• Design verification regression environments and perform functional, RTL code, assertion, and gate-level coverage analysis.
• Collaborate with design engineers, IP developers, and software developers to deliver SoC verification on aggressive schedules.
• Develop best practices and methods for SoC verification.

Requirements

• 5–8 years of digital design verification experience.
• Bachelor’s or master’s degree in computer science, computer engineering, electronics engineering, or electrical engineering.
• Strong debugging, analysis, communication, documentation, and cross-functional collaboration skills.
• Experience with HDL and HVL languages and verification methodologies.
• Experience with ASIC, FPGA, or SoC verification or development cycles.
• Knowledge of Cadence IES/Xcelium, Synopsys VCS, or Mentor Questa, plus Python, Perl or shell scripting, Tcl, and Make.

Culture & Benefits

• Work in a fast-paced, results-oriented, team-first environment.
• Join an international engineering and manufacturing organization focused on R&D, product innovation, and customer service.
• Access a comprehensive compensation and benefits program.
• Participate in a diverse and collaborative workplace.
• Successful background and reference checks are required.