Senior IP Designer Engineer (FPGA)

Location: Penang, Malaysia. The role requires satisfactory proof of the right to work in Malaysia.

Company

hirify.global develops low-power programmable logic solutions, including FPGA, CPLD, and programmable power management devices.

What you will do

• Build Connectivity IP portfolios for Lattice FPGAs.
• Work with architects to translate specifications into high-speed RTL designs.
• Optimize designs for performance, power, and logic utilization.
• Perform FPGA RTL design, logic verification, debugging, and timing closure.
• Support hardware validation, interoperability testing, soft IP packaging, example designs, and testbench development.

Requirements

• BS, MS, or PhD in Electronics or Computer Engineering.
• At least 5 years of FPGA IP design experience.
• Programming skills in C/C++, Perl, TCL, or Python.
• Capability to work independently and execute effectively in a dynamic environment with uncertainty.
• Must provide satisfactory proof of the right to work in Malaysia.

Nice to have

• Experience with high-speed SERDES and video protocols such as HDMI, SDI, DisplayPort, or MIPI.
• Experience in hardware validation or hardware interoperability testing.
• Experience with soft IP packaging, example design, and testbench development.

Culture & Benefits

• Work in an international organization focused on R&D, product innovation, and customer service.
• Collaborate within a team-first, results-oriented environment.
• Access a comprehensive compensation and benefits program.
• Work in a global workforce of approximately 1,000 employees.