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10 часов назад

Senior ATE Test Engineer (AI Infrastructure)

135 500 - 170 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior ATE Test Engineer (AI infrastructure and mixed-signal SoCs): Developing and supporting ATE test solutions for complex mixed-signal silicon SoC products with an accent on test strategy, hardware development, and high-volume production ramp. Focus on high-speed SerDes testing, DFT coverage, ATE bring-up, tester optimization, and debugging PCIe, Ethernet, DDR, NVMe, and USB interfaces.

Location: San Jose, California, United States

Salary: $135,500–$170,000 per year, depending on experience, level, and business need. The role may also include a discretionary bonus, incentives, and benefits.

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and its COSMOS software suite, integrating technologies such as CXL, Ethernet, NVLink, PCIe, and UALink.

What you will do

  • Develop and oversee SoC test strategies and test plans for complex mixed-signal silicon products.
  • Design and develop ATE hardware for wafer sort and final test, including high-speed load boards.
  • Define, implement, and optimize ATE programs and patterns across multiple high-speed tester platforms.
  • Own products from design and initial samples through high-volume manufacturing ramp.
  • Lead silicon and ATE bring-up, bench-to-ATE correlation, debug, and tester resource optimization.
  • Collaborate with design teams and manufacturing partners to maintain product quality and reduce test time.

Requirements

  • Bachelor’s degree in Electrical Engineering; a Master’s degree is preferred.
  • At least 2 years of experience releasing complex SoC or silicon products to high-volume manufacturing.
  • Hands-on experience developing high-speed mixed-signal SoC test programs and hardware on multiple ATE platforms.
  • Strong knowledge of DFT techniques, including SCAN, MEMBIST, SerDes, and functional tests.
  • Experience testing high-speed SerDes operating at 16 Gbps or higher and using the Advantest 93k platform.
  • Proficiency in at least one modern programming language, such as C, C++, or Python, plus experience with protocol analyzers and oscilloscopes.

Nice to have

  • Experience with external loopback at wafer sort.
  • Familiarity with modern databases.
  • Fluency in data processing with high-level programming languages.

Culture & Benefits

  • Work alongside a team of experienced engineers in a high-growth connectivity business.
  • Opportunity to contribute hands-on technical expertise to rack-scale AI infrastructure.
  • Bonus, incentives, and benefits may be available.
  • Applications are encouraged from candidates with diverse backgrounds and experiences.

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