Principal Digital Design Engineer

Location: Munich, Cork, Katowice, or Edinburgh

Company

hirify.global develops electronic design automation software, hardware, and intellectual property for semiconductor and electronic product development.

What you will do

• Design, implement, and integrate high-quality synthesizable RTL using Verilog or SystemVerilog.
• Translate architectural specifications into efficient microarchitectures and RTL for advanced SoCs and silicon platforms.
• Develop unit-level and block-level test environments and debug functional issues using simulation, waveform analysis, assertions, and verification tools.
• Collaborate with architects, verification engineers, physical design engineers, and downstream teams to resolve design and integration issues.
• Support synthesis, timing analysis, linting, CDC analysis, IP integration, and RTL-to-gates implementation flows.
• Document design decisions and contribute to RTL methodologies, automation, development flows, and technical solutions for customer and internal silicon problems.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.
• 10+ years of relevant RTL or ASIC design experience.
• Proficiency in Verilog or SystemVerilog and experience developing synthesizable RTL for ASIC or FPGA implementations.
• Understanding of digital logic, synchronous design, SoC interfaces and protocols, simulation, RTL debugging, synthesis, timing, and physical implementation.
• Ability to analyze complex technical problems, develop practical solutions, communicate effectively with customers, and work within a multidisciplinary engineering team.

Culture & Benefits

• Work at the intersection of advanced semiconductor technology, electronic design automation, and real silicon.
• Influence the full path from design methodology and technology development through to working silicon.
• Collaborate with leading semiconductor companies and technology partners on complex design challenges.
• Travel expected to be less than 10%.
• Opportunities to develop technical leadership across increasingly complex silicon engineering areas.