Physical Design for PPA Optimization Engineer

Location: Haifa, Israel; hybrid work model with time split between the assigned hirify.global site and off-site work

Company

hirify.global develops process technologies and next-generation silicon products.

What you will do

• Optimize power, performance, and area (PPA) for hirify.global IPs.
• Define and implement design-technology co-optimization (DTCO) experiments.
• Develop physical design optimization methodologies for placement, clock-tree synthesis, routing, and timing closure.
• Run the full place-and-route flow to evaluate the impact of new process technologies on PPA metrics.
• Identify device-, cell-, and block-level trade-offs and optimization opportunities.
• Analyze implementation results and provide recommendations that support process, product, and design decisions.

Requirements

• BSc or MSc in Electrical Engineering, Computer Engineering, or a related field.
• Hands-on experience in physical design or circuit design.
• Basic scripting experience with Python, Tcl, or a similar language.
• Strong analytical and problem-solving skills.
• Ability to analyze implementation results and communicate conclusions clearly.
• Full-time hybrid availability in Haifa, Israel.

Nice to have

• 2+ years of experience in physical design or circuit design.
• Familiarity with physical design implementation flows and methodologies.
• Understanding of transistor-, cell-, and block-level PPA trade-offs.
• Experience developing physical design methodologies and analysis tools.

Culture & Benefits

• Hybrid work model combining on-site and off-site work.
• Collaboration with Core and SoC design teams worldwide.
• Work at the intersection of process and design development.
• Shift 1 schedule in Israel.