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4 дня назад

ASIC Synthesis and STA Engineer - New Grad (ASIC)

70 700 - 112 900$
Тип работы
fulltime
Грейд
junior
Английский
b2
Страна
Canada
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
ASIC Synthesis and STA Engineer - New Grad (ASIC): Executing front-end implementation for high-performance optical networking ASIC subsystems with an accent on synthesis, static timing analysis, logical equivalence checking, and clock domain crossing validation. Focus on developing timing constraints, optimizing automation workflows, implementing engineering change orders, and coordinating front-end and back-end activities.

Location: Ottawa, Canada

Annual salary: $70,700–$112,900

Company

hirify.global develops high-speed connectivity infrastructure and optical networking technologies, including the WaveLogic family of ASIC-based products.

What you will do

  • Execute front-end implementation for assigned ASIC IP subsystems, including synthesis, static timing analysis, logical equivalence checking, and clock domain crossing validation.
  • Develop and maintain timing constraints for synthesis, signoff, and subsystem integration.
  • Verify equivalence between RTL and gate-level netlists during pre-layout and post-layout stages.
  • Validate clock domain crossings for top-level ASIC integration.
  • Create and optimize scripts, tools, and documentation to improve synthesis and static timing workflows.
  • Implement engineering change orders and collaborate with ASIC integration, IP development, physical design, and external EDA partners.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related discipline, or equivalent experience.
  • Knowledge of ASIC implementation flows, including synthesis, timing analysis, logical equivalence checking, and clock domain crossing validation.
  • Familiarity with RTL design principles and hardware description languages.
  • Ability to work effectively in multidisciplinary engineering teams and manage deliverables against project schedules.

Nice to have

  • Experience with floorplanning, Design for Testability, place and route, or other front-end and back-end design activities.
  • Experience using synthesis or static timing analysis tools in an ASIC development environment.
  • Exposure to deep-submicron ASIC technologies, advanced timing closure, Python or Tcl scripting, DSP-centric or high-speed ASIC programs, and collaboration with EDA vendors or foundry technology teams.

Culture & Benefits

  • Development opportunities and work focused on high-speed optical networking infrastructure.
  • Medical, dental, and vision plans.
  • Participation in DCPP in Canada with company matching, an Employee Stock Purchase Program, and an Employee Assistance Program.
  • Company-paid holidays, paid sick leave, vacation time, and applicable paid family leave.
  • Potential eligibility for a discretionary incentive bonus.

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