5 часов назад
Technical Staff Engineer - Verification (FPGA)
91 000 - 232 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Technical Staff Engineer - Verification (FPGA): Verifying next-generation, highly secure, low-power FPGA SoC products with an accent on constrained-random, formal, C-based, power-aware, and gate-level methodologies. Focus on developing reusable UVM environments, integrating AI/ML-enabled EDA flows, collaborating on emulation and hardware prototyping, and driving first-silicon success.
Location: Chandler, Arizona, United States
Annual base salary: $91,000–$232,000, plus restricted stock units and quarterly bonus payments.
Company
is a large semiconductor technology company developing products and solutions that power systems worldwide.
What you will do
- Verify complex subsystems and SoCs using constrained-random, formal, and C-based verification methodologies.
- Develop and maintain reusable UVM-based test benches and verification environments.
- Perform RTL, power-aware, gate-level, emulation, hardware prototyping, and post-silicon verification activities.
- Apply AI/ML-enabled verification methodologies and contribute to tool automation and flow integration.
- Collaborate with architecture, design, emulation, and hardware prototyping teams to establish unified verification methods and support first-silicon success.
- Mentor junior verification engineers.
Requirements
- 12.5+ years of functional verification experience with complex SoC designs.
- Expertise in SystemVerilog, UVM, formal verification, methodology development, and tool automation.
- Understanding of ARM or RISC-V SoC architectures and at least two relevant domains, such as CPU subsystems, PCIe, DDR, MIPI, Ethernet MAC, USB, or security and cryptography IP.
- Experience with AI/ML-driven EDA tools, Python, TCL/TK, C/C++, and verification flow integration.
- Exposure to FPGA-based acceleration platforms, simulation and emulation flows, hardware prototyping, and post-silicon debug.
- BS or MS degree in Electrical or Electronic Engineering with 12+ years of experience.
Nice to have
- Strong understanding of FPGA architecture.
- Experience with ML-based coverage-driven verification optimizations.
- Knowledge of the complete SoC RTL-to-GDS-to-silicon release flow.
Culture & Benefits
- Health benefits begin on the first day of employment.
- Retirement savings plans and an employee stock purchase program with a two-year look-back feature.
- Competitive total compensation including base pay, restricted stock units, and quarterly bonuses.
- Work with global cross-functional teams in an environment emphasizing employee development, collaboration, and values-based decision-making.
- Travel requirement of 0%–25%.
Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →
Похожие вакансии
6 дней назад
Senior Design Verification Engineer (SystemVerilog/UVM)
164 470 - 311 890$
6 дней назад
Sr Staff SoC Verification Engineer
135 900 - 201 130$
4 дня назад
Senior SoC Design Verification Engineer
164 470 - 269 100$
6 дней назад
CPU Pre-Silicon Verification Engineer
6 дней назад
ASIC Design Verification Engineer (SystemVerilog/UVM)
129 400 - 207 000$
6 дней назад
Staff SoC Verification Engineer
115 200 - 170 390$