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обновлено 3 дня назад

CPU Pre-Silicon Verification Engineer

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Mexico
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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Описание вакансии

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TL;DR
CPU Pre-Silicon Verification Engineer (CPU/SystemVerilog/UVM): Ensuring the functional correctness and robustness of CPU microarchitecture blocks and top-level subsystems with an accent on constrained-random verification, coverage closure, and assertion-based validation. Focus on building scalable UVM environments, debugging complex RTL and testbench failures, and validating architectural features through simulation and formal methods.

Location: On-site in Guadalajara, Mexico. Permanent, unrestricted right to work in Mexico is required.

Requirements

  • Bachelor's degree or higher in Electrical/Electronic Engineering or Computer Engineering with 5+ years of experience, or a Master's degree with 3+ years of experience.
  • Experience with digital logic design, including instruction set execution, ALUs, control units, registers, memory, and system buses.
  • Programming and scripting experience with SystemVerilog, C++, and at least one scripting language such as Python, Perl, or Tcl.
  • Strong analytical, debugging, and problem-solving skills.
  • Advanced English level and permanent, unrestricted authorization to work in Mexico.

Nice to have

  • Experience with Synopsys simulators.
  • Hands-on experience developing reusable and scalable UVM-based testbenches.
  • Experience defining validation strategies based on architectural and design insights.

What you will do

  • Lead pre-silicon functional verification for complex CPU microarchitecture blocks and top-level subsystems.
  • Develop verification plans covering corner cases, stress scenarios, functional coverage, code coverage, and assertion coverage.
  • Build and enhance scalable UVM-based constrained-random environments, including testbenches, agents, sequences, checkers, and scoreboards.
  • Implement stimulus and SystemVerilog assertion-based verification, and execute block-level and system-level simulations.
  • Debug RTL and testbench failures using simulation tools, waveforms, and formal methods, performing root-cause analysis with architects and designers.
  • Improve verification methodologies and infrastructure, document strategies and results, and mentor junior engineers.

Culture & Benefits

  • Work within a worldwide silicon engineering organization developing and integrating SoCs, CPU cores, and critical IP.
  • Collaborate with architecture, design, post-silicon, performance modeling, formal verification, emulation, and prototyping teams.
  • Full-time experienced-hire position on Shift 1 in Mexico.
  • Employment practices follow local equal-opportunity and ethical hiring requirements; no recruitment or hiring fees are charged.

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