CPU Pre-Silicon Verification Engineer

TL;DR

CPU Pre-Silicon Verification Engineer (UVM/SystemVerilog): Lead and execute pre-silicon functional verification of complex CPU microarchitecture blocks and top-level subsystems with an accent on coverage-driven closure, scalable UVM-based constrained-random environments, and SVA-based validation. Focus on debugging complex RTL/testbench failures with root-cause analysis and collaborating with CPU architects and RTL designers to reduce verification risks and improve methodology and infrastructure.

Company

hirify.global develops and integrates SoCs, CPU cores, and critical IP from architecture through manufacturing readiness.

What you will do

• Lead pre-silicon functional verification against architectural and microarchitectural specifications for CPU blocks and top-level subsystems.
• Develop and maintain verification and test plans, including corner cases, stress scenarios, and coverage goals.
• Architect and enhance UVM-based (or similar) constrained-random verification environments with reusable testbenches, agents, sequences, checkers, and scoreboards.
• Define and implement functional/code/assertion coverage models and drive systematic coverage closure.
• Implement high-quality stimulus and assertion-based verification using SVA; run block-level and system-level simulations.
• Debug RTL and testbench failures using simulation tools, waveforms, formal methods, and collaboration with designers; mentor junior engineers.

Requirements

• Advanced English level (English resume required for consideration).
• Must have unrestricted, permanent right to work in Mexico.
• Bachelor’s degree or higher in Electrical/Electronic Engineering or Computer Engineering (5+ years) or Master’s degree (3+ years).
• Experience with digital logic design (instruction execution, ALUs, control units, registers, memory, system buses).
• At least one scripting language (e.g., Python, Perl, Tcl), plus C++ and SystemVerilog.
• Strong analytical and debugging skills for complex RTL and verification failures.

Culture & Benefits

• On-site presence required in Mexico (Guadalajara).
• Mentorship and best-practice development for verification methodology and tool flows.
• Opportunities to support related activities such as performance modeling, formal verification, emulation, and prototyping.
• Ethical hiring practices with no recruitment fees charged during the hiring process.

Hiring process

• Submit an English resume (multiple versions allowed, but an English version is required).
• Evaluation based on minimum and preferred qualifications for the CPU verification role.

Location: Mexico, Guadalajara (on-site)