Senior Engineer – Verification (ASIC/FPGA)

Location: Dresden, Germany

Company

hirify.global is a global technology organization developing products and solutions that power electronic systems.

What you will do

• Develop and maintain verification plans, methodologies, and environments for complex digital and mixed-signal designs.
• Define verification requirements with design, architecture, and software teams, and resolve issues throughout the product lifecycle.
• Debug failures, identify root causes, and collaborate with design teams on solutions.
• Drive UVM, assertion-based verification, coverage metrics, and verification deliverables.
• Evaluate tools and flows, participate in design reviews, and provide feedback on testability and coverage.
• Communicate project status, risks, and results while mentoring junior engineers.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 8–10 years of experience in ASIC/FPGA verification or a similar role.
• Strong expertise in UVM and SystemVerilog Assertions.
• Strong understanding of digital design, simulation, and debugging tools.
• Experience with Python, Perl, or Tcl scripting for automation.
• Excellent problem-solving, analytical, collaboration, mentoring, and written and verbal English communication skills.

Nice to have

• Mixed-signal verification experience.
• Familiarity with Synopsys, Cadence, or Mentor EDA tools.
• Knowledge of PCIe, Ethernet, USB, or similar industry standards and protocols.
• Experience in safety-critical or high-reliability domains.

Culture & Benefits

• Full-time employment within a large global organization.
• Work on advanced technology with experienced engineering teams.
• Opportunity to influence verification strategies and product quality.
• Professional growth and career advancement support.
• Competitive compensation and benefits package.
• Travel requirement of 0%–25%.