Technical Staff Engineer - Analog Design (SRAM Design)

Location: San Jose, California, United States. Full-time position with usual business hours and 0–25% travel.

Annual base salary: $91,000–$232,000, plus restricted stock units and quarterly bonuses.

Company

hirify.global develops embedded control products including microcontrollers, microprocessors, FPGA devices, mixed-signal and power-management products, connectivity devices, and memory solutions.

What you will do

• Define, develop, and optimize full-custom high-speed SRAM blocks for speed, low power, area, and feature set.
• Develop memory-array architectures supporting redundancy, ECC compliance, yield, and efficient power usage.
• Run memory-compiler experiments and analyze PPA trade-offs across memory configurations and cell types.
• Create and verify circuit schematics and functional Verilog models, using SPICE-based simulation to evaluate stability, margins, retention, noise, timing, and power.
• Design sense amplifiers and SRAM testability circuitry, and define memory test requirements.
• Collaborate with architecture, ASIC, firmware, verification, timing, test, and layout teams through specifications, characterization, and silicon validation.

Requirements

• Bachelor’s degree in Computer Engineering, Electrical Engineering, or Computer Science.
• 12+ years of experience in custom SRAM design and/or memory circuit design.
• High proficiency with SPICE simulation and full-custom design EDA tools.
• Experience with scripting, simulation-queue management, data capture, and analysis.
• Ability to analyze yield, reliability, and power, and to develop and test Verilog simulation models against SPICE-based models.
• Strong analytical, communication, documentation, collaboration, and independent execution skills.

Nice to have

• Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science.
• Experience in analog and full-custom design, FPGA or ASIC development, functional verification, and timing characterization.
• Experience with low-power techniques such as dual rail, array biasing, sleep modes, power gating, and column-array multiplexing.
• Experience with OCV timing and yield-variation analysis using Solido and Monte Carlo methods.

Culture & Benefits

• Health benefits begin on the first day of employment.
• Retirement savings plans and an employee stock purchase plan with a two-year look-back feature.
• Career development through Leadership Passage Programs and employee development initiatives.
• Work involves indoor office and laboratory activities, collaboration with other teams, and independent work.