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7 дней назад

Lead RF Layout Designer (Cadence SKILL)

Тип работы
fulltime
Грейд
lead
Английский
b2
Страна
India
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Lead RF Layout Designer (Cadence SKILL): Developing and implementing RF, analog, and mixed-signal technology test-chip layouts from device-level structures through tapeout and mask ordering with an accent on layout automation, PDK enablement, and manufacturability. Focus on building custom PCells and Cadence SKILL frameworks, solving DRC/LVS, yield, and reliability challenges, and leading cross-functional technology development.

Location: Bengaluru, Karnataka, India

Company

hirify.global manufactures advanced semiconductors for high-growth markets, with operations across the United States, Europe, and Asia.

What you will do

  • Lead end-to-end layout implementation for technology development test chips, including device test structures, circuit test vehicles, tapeout, and mask order execution.
  • Develop custom PCells and layout automation solutions using Cadence SKILL scripting.
  • Create RF, analog, and mixed-signal layouts for technology development, characterization, and qualification.
  • Collaborate with device, process, modeling, design, and CAD/PDK teams to define and validate design rules, layout methodologies, and technology enablement strategies.
  • Resolve complex layout, manufacturability, reliability, and yield challenges during technology development and productization.
  • Provide technical leadership and mentorship while coordinating small multidisciplinary project teams.

Requirements

  • At least 10 years of experience in layout design, layout automation, and semiconductor technology development.
  • BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.
  • Expert-level Cadence SKILL programming experience, including complex layout automation frameworks and custom PCell development.
  • Hands-on experience with Cadence Virtuoso, custom layout design, PCell development, layout verification, and semiconductor testsite automation.
  • Understanding of semiconductor process technologies, design rules, manufacturability, reliability, and yield.
  • Experience with test-chip development, DRC/LVS closure, tapeout execution, mask release, PDK development, and technology enablement.

Culture & Benefits

  • Work within a multicultural, inclusive, and global engineering organization.
  • Collaborate across international design, process, device, modeling, and CAD/PDK development groups.
  • Benefits are provided according to the applicable local employment terms and regulations.

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