Sr Staff / Principal CAD & Design Methodology Engineer (RTL-to-GDSII)

Location: Bay Area; on-site.

Company

hirify.global develops advanced SoC and chiplet products requiring multi-node RTL-to-GDSII design infrastructure.

What you will do

• Architect, develop, and maintain hierarchical RTL-to-GDSII implementation flows for complex SoC designs using top-down and bottom-up methodologies.
• Build a vendor-agnostic platform integrating Synopsys, Cadence, and Siemens EDA tools across Intel Foundry, TSMC, Samsung, and GlobalFoundries nodes.
• Define the Reference Design and Validation Platform, design rules, constraint templates, implementation guidelines, and foundry-specific methodology through tapeout.
• Lead low-power core methodology, including UPF/CPF flows, multi-voltage domains, level shifters, isolation, retention, power-domain verification, EM/IR, and PDN strategies.
• Define hierarchical planning, floorplanning, partitioning, timing budgets, pin constraints, timing models, clocking architectures, synthesis, DFT integration, and STA methodology.
• Drive CAD infrastructure improvement through automation, ML-assisted optimization, and emerging EDA capabilities while working with foundry technology teams.

Requirements

• 15+ years of experience in ASIC CAD, design methodology, or physical design, with a record of leading multi-node, multi-foundry platform deployments.
• Experience deploying RTL-to-GDSII platforms across external foundry nodes including TSMC N3/N5/N7, Samsung SF3/SF4, and GlobalFoundries GF12/GF22.
• Deep expertise in low-power design methodology, including UPF/CPF flows, multi-voltage domain integration, retention strategy, and power-domain verification.
• Expertise in Clock Mesh, Spine-and-Rib, H-Tree, and hybrid clock architectures with custom cell integration.
• Familiarity with chiplet and 2.5D integration, die-to-die interface timing, UCIe/BoW PHY integration, and hierarchical top-level assembly flows.
• Exceptional problem-solving and communication skills, including presenting to executive leadership and engaging directly with foundry technology teams.

Culture & Benefits

• Full-time, on-site engineering role in the Bay Area.
• Work directly with foundry technology teams and external EDA ecosystem partners.
• Final hiring decisions are made by humans; AI tools may support application review and assessment.