FPGA Post Silicon Validation Engineer - HPS USB (FPGA)

Location: Penang 15, Penang, Malaysia

Company

hirify.global develops FPGA SoC devices and related semiconductor technologies.

What you will do

• Develop and execute post-silicon validation strategies for HPS USB subsystems, including USB 2.0/3.x host, device, OTG, hub, and peripheral interoperability scenarios.
• Bring up and debug HPS subsystems, covering USB connectivity, protocol compliance, reset sequencing, clocking, PHY initialization, and hardware-software interactions.
• Create test plans for protocol validation, interoperability, stress, performance, negative, and corner-case testing.
• Use protocol analyzers, oscilloscopes, logic analyzers, JTAG debuggers, and USB compliance tools to investigate silicon issues.
• Drive root-cause analysis and issue triage across silicon, firmware, software, and platform components.
• Build automation frameworks and regression environments with Python, TCL, Bash, or similar scripting languages, while collaborating with architecture, firmware, design, and board teams.

Requirements

• Bachelor’s or Master’s degree in Electrical and Electronics Engineering, Computer Engineering, Computer Science, or a related field.
• 8+ years of post-silicon validation experience focused on SoC, HPS, USB, or high-speed I/O subsystems.
• Strong understanding of USB 2.0/3.x architecture, protocol layers, enumeration, link training, power management, and compliance requirements.
• Experience validating embedded processor subsystems, boot loaders, Linux environments, device drivers, memory bring-up, and peripherals.
• Strong hardware and software debugging skills, including experience with USB protocol analyzers and validation laboratory equipment.
• Proficiency in Python, TCL, or similar scripting languages for automation and test infrastructure development.

Nice to have

• Familiarity with FPGA SoC architectures and embedded systems.

Culture & Benefits

• Regular full-time employment.
• Shift 1 schedule in Malaysia.
• Cross-functional collaboration with architecture, firmware, design, platform, and board teams.