DFT Engineer (ASIC)

Location: Cambridge, England, United Kingdom; on-site

Company

hirify.global develops its own silicon, including microcontrollers and platform chips, through specification, design, verification, implementation, ATE test, and qualification.

What you will do

• Create, implement, and verify DFT solutions for future hirify.global ASIC designs.
• Define DFT strategies at chip, subsystem, and IP level using structural and functional methods.
• Use Tessent flows to insert MBIST, EDT, SSN, scan controls via IJTAG, and IP tests using ICL/PDL in flat and hierarchical designs.
• Verify DFT structures and debug related issues, including timing, power, formal equivalence, and UPF-related issues.
• Support DFT through implementation and sign-off, including generating timing constraints.
• Share knowledge, contribute to the wider team, and mentor or coach other team members.

Requirements

• Experience with IC development flows and Tessent DFT tools.
• Good understanding of complex DFT IP issues, including on-chip clocking.
• Experience in ATPG, MBIST, and simulation debug, including UPF-related issues.
• Good scripting skills, including TCL.
• Willingness to contribute and share activities with the wider team.
• Degree in electronic engineering, computer science, or a related discipline.
• Proactive approach to troubleshooting and ability to coach other team members.

Nice to have

• Understanding of advanced silicon technologies and fault models.
• Familiarity with test access standards such as IJTAG/IEEE 1687.
• Familiarity with vector translation and bring-up on ATE platforms.

Culture & Benefits

• Full-time, on-site work within the Engineering department.
• Competitive salary based on experience level.
• Employer pension contribution of 8% when contributing 4% of gross salary through the salary sacrifice scheme.
• Life assurance of four times base salary and income protection of 75% of base salary after 13 weeks of long-term illness or absence.
• Private medical insurance with medical history disregarded.
• Electric vehicle salary sacrifice scheme, subject to eligibility.