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7 дней назад

Staff Engineer, SoC Architecture – Memory Subsystem and Interconnect

179 200 - 246 150$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Staff Engineer, SoC Architecture – Memory Subsystem and Interconnect (Fabric, System Cache, DRAM Controller): Architecting next-generation SoCs and developing memory subsystem and interconnect features with an accent on performance, power, bandwidth, latency, and area tradeoffs. Focus on high-level performance modeling, memory scheduling and QoS analysis, ARM bus infrastructure, JEDEC memory standards, and guiding microarchitectural proposals through silicon bring-up.

Location: Onsite at 665 Clyde Avenue, Mountain View, California, USA

Base pay range: $179,200–$246,150 USD annually, plus annual bonus eligibility and benefits.

Company

hirify.global develops SoC architecture, bus and memory subsystems, multimedia subsystems, and IP blocks for Samsung Galaxy products and future devices.

What you will do

  • Lead architecture and microarchitecture development for Fabric, System Cache, and DRAM Controller subsystems.
  • Develop proposals that improve power and performance across targeted workloads and product markets.
  • Perform high-level performance modeling, simulation, benchmarking, and use-case analysis.
  • Deliver architecture and microarchitecture specifications to hardware and software design teams.
  • Communicate tradeoff analyses and recommendations across software, hardware, architecture, and leadership audiences.
  • Collaborate with silicon bring-up and product teams to verify and debug delivered performance across the SoC, drivers, and operating system.

Requirements

  • Bachelor’s, master’s, or doctoral degree in Computer Science, Computer Engineering, or equivalent education and experience.
  • 8+ years of experience in SoC or ASIC design and architecture.
  • More than 5 years of direct experience in Fabric, System Cache, DRAM Controller architecture, or microarchitecture.
  • Strong understanding of memory controller architecture, memory scheduling, prioritization, and QoS.
  • Detailed knowledge of ARM bus infrastructure, including ACE, AXI, and AHB.
  • Knowledge of JEDEC standards such as LPDDR, DDR, or HBM, with the ability to analyze standards and develop recommendations.

Nice to have

  • Experience with BookSim Simulator.
  • Experience with Platform Architect.

Culture & Benefits

  • Comprehensive compensation package with annual bonus eligibility.
  • Generous employee benefits.
  • Inclusive workplace and equal employment opportunity for qualified applicants.
  • Reasonable accommodation available during the employment selection process.

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