Junior Logic Design Engineer (FPGA)

Location: Haifa, Israel; Shift 1 (Israel)

Company

hirify.global develops programmable FPGA, CPLD, and IP solutions for high-speed connectivity, AI acceleration, and data infrastructure from cloud to edge.

What you will do

• Assist with logic design, RTL development, and simulation for IP blocks, functional units, and subsystems.
• Support architectural and microarchitectural discussions and implementation under the guidance of senior engineers.
• Apply mixed-signal concepts, basic analog behavior modeling, and circuit simulation to RTL development and optimization.
• Help optimize designs for power, performance, area, and timing requirements suitable for physical implementation.
• Participate in RTL verification, review test results, and debug failing tests.
• Collaborate with internal teams and support SoC customers during IP integration and delivery.

Requirements

• 0–2 years of experience in logic design, digital design, or a related field; internships, co-ops, and academic projects count.
• Good understanding of digital design fundamentals, RTL, Verilog/SystemVerilog, and simulation concepts.
• B.Sc. or upcoming graduate in Electrical Engineering or a related field.
• Strong problem-solving skills and willingness to learn in a collaborative environment.
• Applicants must include an academic grades sheet or transcript with the application.

Nice to have

• Familiarity with communication interfaces or high-speed design concepts.
• Exposure to mixed-signal concepts, SerDes, PHYs, or signal processing through coursework or projects.

Culture & Benefits

• Regular full-time employment.
• Collaboration with experienced engineers in a fast-paced environment.