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8 часов назад

Senior ASIC Design Engineer

Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Israel
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Senior ASIC Design Engineer (AI Connectivity Hardware): Designing complex digital ASIC blocks for AI infrastructure connectivity, from high-level definition and micro-architecture through RTL implementation, debug, and backend support, with an accent on high-performance, power-efficient hardware. Focus on meeting PPA targets, applying EDA-based quality checks, supporting deep-submicron designs, and improving design automation workflows.

Location: Israel

Company

hirify.global develops semiconductor-based connectivity solutions and software for rack-scale AI infrastructure, integrating technologies such as CXL, Ethernet, NVLink, PCIe, and UALink.

What you will do

  • Own digital logic blocks from high-level definition and micro-architecture through RTL coding, debug, and backend implementation support.
  • Design high-performance hardware solutions for complex AI infrastructure connectivity requirements.
  • Act as the primary point of contact for assigned logic blocks while collaborating with Architecture, Verification, and Backend teams.
  • Use lint, CDC, synthesis, timing, power, and internal quality-assurance tools to improve design robustness and efficiency.
  • Apply design techniques to meet power, performance, and area targets.
  • Contribute to design methodology improvements, tool automation, verification, validation, and AI-assisted engineering workflows.

Requirements

  • Bachelor's degree in Electrical Engineering or a related technical field.
  • 3+ years of logic-design experience at semiconductor companies.
  • Knowledge and experience with Verilog and/or SystemVerilog.
  • Understanding of digital design principles and RTL coding best practices.
  • Excellent communication skills and the ability to collaborate effectively across teams.

Nice to have

  • Master's degree in Electrical Engineering or a related field.
  • Knowledge of DDR and PCIe protocols and their implementation.
  • Experience with power-management techniques, clock-domain crossing, simulation, debugging, synthesis, and timing analysis.
  • Proficiency in Python or Perl scripting.
  • Experience with high-speed serial interface designs or connectivity protocols.

Culture & Benefits

  • Opportunity to join a new strategic R&D center in Israel and help build its engineering organization.
  • Product ownership across the ASIC design lifecycle.
  • Collaboration with architecture, verification, backend, hyperscaler, and ecosystem partners.
  • Inclusive workplace that encourages applications from people with diverse backgrounds and experiences.

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